Abstract: A resistor mirror which biases transistors substantially in their linear region of operation and in such a way that their combined parallel resistance is equal to the resistance of a reference resistor. The resistor mirror may include three or more offset control circuits, a feedback control circuit with a reference resistor, a reference voltage-controlled resistor, and one or more additional voltage-controlled resistors. The offset control circuit includes two voltage-controlled current sources. Three or more offset control circuits are connected in a manner so as to affect an equal number of resistor control output terminals coupled to the reference voltage-controlled resistor and to the additional voltage-controlled resistors. To minimize signal coupling between multiple voltage-controlled resistors coupled to the same resistor control output terminals, and to insure stability in the circuit's operating point, a filter capacitor is coupled to each resistor control output terminal.

Abstract: The present invention comprises baluns 2a, 2b which convert balanced line signals and unbalanced line signals mutually, and filters 3a, 3b which are electrically connected to the baluns 2a, 2b and pass or attenuate the predetermined frequency bands. Electrode layers 15a-22a, 25a, 41, 42, 43 which compose the electrode patterns of the baluns 2a, 2b and the filters 3a, 3b, and the dielectric layers 30-39 are integrally stacked.

Abstract: A technique for deskewing digitizer channels in an automatic test system includes applying a waveform of known frequency to the input of each digitizer channel. Each digitizer channel samples the waveform to produce a respective data record. A Discrete Fourier Transform (DFT), or a portion thereof, is then taken for each data record to determine, at minimum, the phase of the waveform. Phase differences across different digitizer channels are converted to time differences, which values are applied to subsequent digitizer measurements to correct for timing skew. Because a large number of samples in a digitizer's data record contribute to the computed phase of the waveform, the effects of timing jitter are substantially eliminated from skew measurements, without the need for repeating measurements and explicitly averaging results.

Abstract: A surface acoustic wave duplexer includes a branching section having a plurality of surface acoustic wave filters provided on a first electrode pattern on the front surface of a multi-layer substrate. An antenna terminal, a transmission terminal, and a receiving terminal are provided on peripheral portions of a fourth electrode pattern on the rear surface of the multi-layer substrate, and are connected to the branching section. A matching stripline disposed on a third electrode pattern in an intermediate layer of the multi-layer substrate, and connected to the antenna terminal is arranged such that it is grounded to at least one side other than the side opposite the side where the antenna terminal is located.

Abstract: The invention provides a surface acoustic wave device which uses an in-plane rotated ST cut quartz crystal plate around the Z′-axis, and which has a large reflection coefficient of the Rayleigh wave. Comb teeth-like IDT electrodes are provided and reflectors to trap the Rayleigh wave are provided on both sides of the IDT electrodes on the principal surface of the in-plane rotated ST cut quartz crystal plate. The electrode width and pitch at the IDT electrodes are defined as Lt, Pt, the width and pitch of short-circuit electrodes at the reflectors as Lr, Pr, and the thickness of the IDT electrodes and the short-circuit electrodes side as Ht and Hr. If the electrode widths and pitches are set up so that either or both of Lt/Pt and Lr/Pr become 0.32±0.1, this enables maximizing the reflection coefficient and achieving the miniaturization of device itself by reducing the number of the short-circuit electrodes.

Abstract: A multiplexer that can be used, for example, in a programmable logic device (PLD). The multiplexer includes a plurality of pass transistors passing a selected one of several input values to an internal node, which drives a buffer that provides the multiplexer output signal. The pass transistors can be controlled, for example, by values stored in memory cells of a PLD. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The buffer includes transistors having a second and thinner oxide thickness, and is operated at a second and lower operating voltage. Where memory cells are used to control the pass transistors, the memory cells include transistors having the first oxide thickness and operate at the first operating voltage. Some embodiments also include transistors of varying gate length for each of the pass transistors, buffer transistors, and memory cell transistors.

Abstract: The present invention provides a fault-tolerant inverter circuit, comprising a signal input point for receiving the input signals. A first inverter, the input end of the first inverter connects to the signal input point. A second inverter, the input end of the second inverter connects to the output end of the first inverter. A third inverter, the input end of the third inverter connects to the output end of the second inverter. A signal output point, and it is used to connect the output end of the third inverter. A first conducting wire, the two ends of which connect respectively to the signal input point of the first inverter and the output end of the second inverter. A second conducting wire, the two ends of which connect respectively to the outputting end of the first inverter and the signal output point. Therefore, the fault-tolerant inverter of the present invention provides fault-tolerance when an opening occurs in any conducting wire or transistor.

Abstract: A current sampling half-bridge output driver capable of driving a wide range of loads using an accurate selection of current sensing resistors. Pluralities of stages are connected in series with the current sensing resistors from each stage connected in series. A range selector selects the stage appropriate for each current load. The reference resistors for a selected stage includes the current sensing resistor associated with that stage added in series to all current sensing resistors electrically connected between the selected stage and the load. The disclosed circuit avoids switching resistors in and out of the circuit and thereby increases the accuracy of the sensing resistor circuit.

Abstract: The waveguide polarizer is a device for microwave antenna systems consisting of a waveguide section, with circular cross-section, being equipped with two terminal flanges for connection to other circular guides. A certain number of elliptical irises are arranged inside at regular intervals, resting on parallel planes and all oriented in the same way, i.e. with their longer axes all belonging to the same axial plane.

Abstract: Clocked full-rail differential logic circuits with sense amplifier and single-rail logic are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock. In Addition, according to the invention, the complementary logic function of the prior art is replaced by a single transistor appropriately sized to provide the complementary output. Consequently, the clocked full-rail differential logic circuits with sense amplifier and single-rail logic of the invention are smaller, less complex and are capable of operating efficiently under heavy load conditions without the increased size and the significant reduction in speed associated with prior art full-rail differential logic circuits.

Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes a bottom clamping transistor coupled to a first potential having a bottom clamping transistor control node arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes a top clamping transistor coupled to a second potential having a top clamping transistor control node arranged for clamping the signal at about a second reference voltage as well as an inverter unit coupling the transmission line to stabilizing capacitors for stabilizing control node voltages.

Abstract: Device interconnects and methods of making the same are described. In one aspect, a device interconnect system includes a bonding pad portion and a transmission line portion. The bonding pad portion is disposed on a device substrate and is constructed and arranged for electrical connection to a bond wire. The transmission line portion is disposed on the device substrate and is constructed and arranged to electrically couple the bonding pad portion to a device formed on the device substrate. The transmission line portion has a width dimension that is substantially parallel to the device substrate and a height dimension that is substantially perpendicular to the device substrate. The width dimension and the height dimension of the transmission line portion both vary from the bonding pad portion to the device.

Abstract: In a conversion sequence for converting an analog input voltage into a digital signal, a redundant comparison cycle is provided to comparison cycles for performing a prescribed number of times of comparison. This redundant comparison cycle may be added after the prescribed number of comparison cycles, or may be inserted into a normal comparison cycle. Such a redundant comparison cycle adds a convergence period of a converted value to the analog input voltage. Accordingly, the final conversion result can be accurately generated even if an error is generated in the conversion sequence. As a result, a successive approximation type analog to digital converter capable of rapidly performing analog-to-digital conversion with high accuracy is implemented.

Abstract: A wireless communication device comprises a power amplifier configured to amplify a power level of a transmit signal to a required transmit power level and a transmission line coupled with the power amplifier. The transmission line is configured to convey the amplified transmit signal. The wireless communication device also comprises a power control circuit that includes a bi-directional coupler detector coupled with the transmission line. The bi-directional coupler detector is configured to sense a forward power level and a reflected power level in the transmission line. The power control circuit may be configured to adjust the required transmit power level based at least in part on the forward and reflected power levels sensed by the bi-directional coupler detector. The power control circuit may also adjust an impedance of an impedance matching circuit based at least in part on the reflected power level sensed by the bi-directional coupler detector.

Abstract: A significant part of the cost of a base station in the cellular mobile radio system is the power amplifier. Thus it is desirable to maximise usage of a power amplifier and in particular to gain the best power output from the amplifier or to improve its efficiency. Such power amplifiers, however, must operate within strict spectral boundaries and thus power amplifiers are typically over-specified in order to ensure that the spectral requirements are met. By measuring the output of the amplifier and determining distortion factors and then adaptively adjusting the operating characteristics of the amplifier, the degree of over-specification of the amplifier required may be reduced with consequent cost and environmental savings.

Abstract: One embodiment of the present invention provides a system that transmits a stream of datawords through a bundle of conductors with a three-dimensional structure. Upon receiving a dataword to be transmitted, the system uses an encoding function to encode the dataword into a current codeword in a stream of codewords, wherein the current codeword is less than double the size of the dataword. Next, the system transmits the current codeword to a destination through the bundle of conductors. Note that the encoding function depends on a preceding codeword in the stream of codewords, so that when the preceding codeword changes to the current codeword, rising transitions are substantially matched with falling transitions within the bundle.

Abstract: Signal sampling is performed. A sampler takes samples of a sampled signal. A first analog-to-digital (A/D) converter receives the samples from the sampler. A clock reference is synchronous with the sampled signal. A phase comparator produces a difference value that indicates a phase difference between the clock reference and an oscillating signal. A second A/D converter receives the difference value. The oscillating signal is used in controlling when the sampler takes samples of the sampled signal.

Abstract: Systems and methods of converting data streams from one clocking domain to another are described. In one aspect, a clocking domain conversion system includes an input, an output, a routing circuit, and a clock generator. The input is operable to simultaneously load N input bits during each load cycle at an average rate RIN, wherein N has an integer value of at least 1. The output is operable to simultaneously output M output bits during each output cycle at an average rate ROUT, wherein M has an integer value of at least 1 and M≠N.

Abstract: A data processor is composed of a register file including a plurality of registers each of which stores therein an operand data, a register pointer section which includes a plurality of register pointers, an instruction register, a data type converter unit, and a processing unit. Each of the register pointers stores therein a register address and a data type of the operand data stored in the register specified by the register address. The instruction register fetches an instruction word including an operation code, and an operand field. The operand field is representative of a register pointer address used for addressing a selected one of the register pointers to thereby indirectly addressing a selected one of the register.

Abstract: A broadband impedance matching circuit for use with an optical device such as an electroabsorption optical modulator comprises a microstrip transmission line, including pairs of like-sized open stubs disposed on opposite sides of the transmission line along its length. The number of open stubs, as well as their dimensions and location are chosen to provide for broadband impedance matching (from dc to several GHz) between an external electrical signal source and the optical device.