Abstract: The invention concerns a demodulator of an amplitude-modulated signal (Vdb), characterised in that it comprises a peak detecting cell (DCR) capable of extracting the reference modulating signal (Vpeak1) of the modulated signal (Vdb); a first demodulator (FE) adapted to detect the peak of the reference modulating signal (Vpeak1) to generate a high comparison threshold and locate the start of the modulation, a second demodulator (RE) adapted to detect a trough of the reference modulating signal (Vpeak1) to generate a low comparison threshold and locate the end of the modulation; a logic processing unit capable of supplying the demodulated signal (Vdemod).

Abstract: A system for detecting and identifying the identity of a base station or cell which transmits a scrambling code is provided. According to one aspect of the system, the system is used to perform scrambling code detection of eight (8) primary cells (each scrambling code's X-component being spaced sixteen (16) chips apart) in a group. According to another aspect of the system, a single scrambling code generator is used to generate a master scrambling code. The master scrambling code is then used to create individual scrambling codes which are used in correlation with received signals to detect in parallel which one of the eight (8) possible primary cells in the group transmitted the received signals. According to yet another aspect of the system, each of the correlators maintains a corresponding X-component segment of the master scrambling code.

Abstract: A transmit diversity system having at least four antennas. A first adder adds a first spread signal obtained by spreading a first symbol pattern with a first orthogonal code to a second spread signal obtained by spreading the first symbol pattern with a second orthogonal code, and transmits the added signal through a first antenna. A second adder adds the first spread signal to a third spread signal obtained by spreading an inverted symbol pattern of the first symbol pattern with the second orthogonal code, and transmits the added signal through a second antenna. A third adder adds a fourth spread signal obtained by spreading a second symbol pattern with the first orthogonal code to a fifth spread signal obtained by spreading the second symbol pattern with the second orthogonal code, and transmits the added signal through a third antenna.

Abstract: A clock regeneration scheme for a digital communication receiver has a first-in, first-out (FIFO) storage buffer into which received data is clocked in accordance with an input clock signal and a data valid signal. A fixed fractional delay line is coupled to provide respectively different phase delayed versions of the input clock signal and feeds a multiplexer that is controllably operative to couple one of the outputs of the fixed fractional delay line to a regenerated clock output port. A control loop, which includes the FIFO storage buffer, the output port and a steering control input of the multiplexer circuit, is operative to selectively change which output of the fixed fractional delay line is coupled by the multiplexer to the output port, so as to controllably cause the output clock signal to track the effective frequency of the valid data signal.

Abstract: Methods and apparatus for canceling co-channel interference in a receiving system using spatio-temporal whitening. In some embodiments, a spatio-temporal interference canceling method, and apparatus for carrying out the method are provided which effectively cancel co-channel interference despite frequency offset between the desired signal and the interferer in a TDMA type system. Real and imaginary component values of the total received signal are used for virtual diversity branches, and a vector-valued auto regressive model is used to characterize the interference. In other embodiments, spatio-temporal interference whitening is used to improve timing estimates used for synchronization. The two uses of spatio-temporal whitening can be combined in one receiver. The invention is typically implemented in one or more programmed digital signal processors or application specific integrated circuits (ASICS), embodied in a receiving system.

Abstract: The transfer function of a filter processing unit is defined by a set of filter coefficients that are continually updated in a coefficient-updating unit. The level of the output signal is adjusted by a level-adjustment unit where, if the largest filter coefficient exceeds an upper threshold value or is below a lower threshold value, a comparator outputs control signals to coefficient-based shifters and to a data signal shifter such that these shift their applied bit sequences in opposite directions and thus multiply or divide the applied data signals by a factor?2.

Abstract: A deskew circuit utilizing a coarse delay adjustment and fine delay adjustment centers the received data in a proper data window and aligns the data for proper sampling. In one scheme, bit state transitions of a training sequence for SPI-4 protocol is used to adjust delays to align the transition points.

Abstract: A novel amplitude deviation correction circuit which corrects an amplitude deviation between an I signal and a Q signal is disclosed. An average amplitude deviation between an I signal amplified by a variable gain amplifier and a Q signal amplified by another variable gain amplifier is detected by an amplitude comparison circuit, and +1 volt or ?1 volt is outputted in response to a result of the detection. An integration circuit integrates the output of the amplitude comparison circuit and controls the gains of the variable gain amplifiers in response to a result of the integration.

Abstract: A method and system characterize a random component of the jitter by designating an edge in the repetitive pattern, determining a slope of the designated edge, and acquiring a set of amplitude values at a different occurrences of the designated edge. A frequency domain representation of the set of amplitude values is then obtained, and identified peaks in the frequency domain representation are truncated. An RMS value, or other measure of random variations of the truncated representation is extracted and converted, based on the slope of the designated edge, to a corresponding RMS time jitter that represents the random component of the jitter. A periodic component of the jitter is characterized by determining the peak amplitude deviation of the acquired set of amplitude values, and then determining a periodic amplitude variation based on the RMS value, the peak amplitude deviation and the number of amplitude values in the set of amplitude values.

Abstract: A method and apparatus for a multicarrier receiver circuit with guard interval size detection is described. The invention allows the FFT size and guard interval size to be detected quickly, even in the presence of relatively noisy input signals. The method is robust in noisy environments, and also sufficiently robust to process signals having severe multipath and/or co-channel interference. Moreover, the method is of low complexity, and can be implemented in a VLSI circuit.

Abstract: An arrangement for generating a clock signal. Embodiments provide a method, apparatus, system, and machine-readable medium to interpolate phases of a reference clock signal to output an interpolated clock signal. Some embodiments may output the clock signal as a recovered clock signal for a phase interpolator-based clock recovery system. Many embodiments may interpolate a changing phase of an interpolated clock signal with substantially analog transitions.

Abstract: All digital reference frequency locking. An all digital approach is provided for operation within one or more CMs within a cable modem communication system to lock the upstream of the one or more CMs to the downstream symbol clock provided from a CMTS. The locking of the CM's upstream may be performed using one of at least three different functions: (1) Locking the upstream symbol clock phase to the downstream symbol clock phase, (2) Locking the downstream symbol clock phase to the headend reference clock phase (typically 10.24 MHz or integer multiple thereof), and (3) Locking the upstream carrier frequency to the downstream symbol clock frequency. The all-digital techniques for supporting all digital reference frequency locking functionality provide high performance to support S-CDMA and other synchronous modulation techniques.

Abstract: The invention relates to a method of performing channel simulation and a channel simulator. The channel simulation is performed digitally. At least a section of a signal (206) to be fed to simulation is transformed by convolution transformation from time space to transformation space in tansformation means (200) of the channel simulator. In weighting means (202), the transformed signal (208) is weighted by a channel impulse response that is transformed from time space to transformation space. Finally, the resulting signal (210) is inverse-transformed in inverse-transformation means (204) to time space.

Abstract: A Wideband Code-Division Multiple Access (WCDMA) transceiver and a method of operating the same. In one embodiment, the transceiver includes: (1) a transmit chain having a lookup table that provides coefficients to a digital predistorter based on power indicators and (2) a predistorter training circuit, coupled to the transmit chain, that employs a receive chain of the WCDMA transceiver to provide a digital compensation signal that is a function of an output of the transmit chain and employs both the power indicators and the digital compensation signal to cause the lookup table to provide alternative coefficients to the digital predistorter thereby to reduce distortion in the output.

Abstract: Systems and methods for correcting phase ambiguity in a total pilot phase value are presented. Examples include comparing and correcting total pilot phase values having different pilot frequencies within the same sampling interval, such as the same data symbol. Another example includes correcting a total pilot phase value for one sampling interval and corresponding to one pilot frequency using nonlinear filtering of values of the total pilot phase for prior sampling intervals at the same pilot frequency.

Abstract: A novel method for generating an interference matrix S is disclosed. The method comprises the following steps: A) Determining the number of active channels N in a transmitter; B) Selecting the transmitter to be canceled and assigning the transmitters sequentially to the variable t; C) Selecting the channel to be cancelled and assigning the channels sequentially to the variable n, where n is less than or equal to N; D) Determining if a multipath signal should be canceled and assigning the multipaths of interest to the respective variable M; E) Generating a sequence of column vectors V; F) Repeating steps B, C, D, E, F and G for each column vector of interest; and G) Defining the S matrix as S=[V1 V2 . . . Vc] wherein the index denotes the column index c. In addition, an apparatus for generating the interference matrix is also disclosed.

Abstract: A waveform having an amplitude that varies to thereby represent corresponding data values is dithered to further shape the waveform so that use of the dithered waveform to create a corresponding FSK signal will result in a signal having a smoothed frequency domain profile. In various embodiments, the waveform amplitude is varied with respect to periodicity of variation, extent of variation, and duration of variation.

Abstract: A second is counted at a step S11, and an information table is read at a step S12. Content change of the information table is checked at a step S13. The content change is checked by checking the value of a CRC or checking content change of at least one of values of PIDs of an image, a sound and a PCR, stream types and descriptors, information necessary for operations of a receiver. When the contents of the information table are determined as changed by the aforementioned checking method (YES at the step S13), a determination is made that change of a program is detected at a step S14 and a program parameter described in the information table is set as a signal extraction parameter of a demultiplexer at a step S15, for executing channel changing validating the signal extraction parameter set in the demultiplexer at a step S16. Thus obtained is a digital broadcast receiving system capable of executing receiving in program change with no hindrance through a receiver having a relatively simple structure.

Abstract: An arrangement for a phase interpolator based clock recovery system, a phase interpolator, and a voltage controller for a highly linear phase interpolator system is provided. Embodiments comprise a method, apparatus, system, and machine-readable medium to recover a clock signal for clocked data based on a local clock signal. In some embodiments, the local clock signal may also be used to transmit the clocked data.

Abstract: A system including base stations and a mobile station that performs a three-stage cell search process. Each base station includes a transmission unit using at least one carrier frequency for transmitting a perch channel signal, in which the at least one carrier frequency is uniquely distinguishable from carrier frequencies used by other base stations. The mobile station performs a first-stage search of the three-stage cell search and represents a search of a plurality of carrier frequencies; performs a second-stage search of the three-stage cell search and represents a search of a specified carrier frequency; performs a third-stage search of the three-stage cell search and represents a search of said specified carrier frequency; and includes a controller selecting the highest strength or highest correlation value carrier frequency among the carrier plurality of carrier frequencies based on a result of the first-stage search to set the selected carrier frequency as said specified carrier frequency.