Abstract: A digital matched filter receives an input signal in natural order, correlates the input signal against a code and generates a filtered output signal in a permuted order with respect to the input signal. The code is a factorization of a first and second patterns. The filter includes a first filter to correlate against the first code and a second filter to correlate against the second pattern. A memory is included to store intermediate values produced from the first filter correlation operation. Certain ones of the intermediate values are selectively retrieved from memory in accordance with a unique addressing scheme for each second filter correlation operation. More specifically, the addressing scheme allows retrieved intermediate values to be reused in successive second filter correlations. The permuted order outputs of the filter are of no concern in many applications, like cell searching, where buffering is available.

Abstract: A receiver detector of a peripheral device for use in a computer system to detect whether a receiver is electrically coupled to a data port of the peripheral device includes a modulator, a high pass filter, and a demodulator. The modulator is configured to modulate a receiver detect signal at a frequency that is higher than a noise frequency, below which high amplitude noise can develop. The high pass filter is electrically coupled to the receiver detect signal and is configured to block frequencies of the receiver detect signal that are below the noise frequency and pass a filtered receiver detect signal. The demodulator is configured to demodulate the filtered receiver detect signal and produce a recovered receiver detect signal that is indicative of whether a receiver is electrically coupled to the data port.

Abstract: A method and device are described for generating two output signals (I; Q) each substantially identical to a square-wave input signal (A) from a local oscillator (2), wherein the first output signal (I) may have a certain time shift with respect to the input signal (A), and wherein the second output signal (Q) is shifted over T1/4 [mod T1] with respect to the first output signal (I), T1 being the period of the input signal (A). To generate the first output signal (I), Fourier components (S1(?1), S3(?3), S5(?5), S7(?7), S9(?9), S11(?11) etc) of the input signal are combined. To generate the second output signal (Q), Fourier components (S1(?1), S5(?5), S9(?9) etc) of the input signal are phase shifted over +90° while Fourier components (S3(?3), S7(?7), S11(?11) etc) of the input signal are phase shifted over ?90°, and the thus shifted Fourier components of the input signal are combined.

Abstract: An asymmetric digital subscriber loop modem may achieve efficiency and cost reduction by providing a coder/decoder (codec) chip which transmits data externally of the chip when the data is at a reduced or lower data rate. That is, instead of transmitting the data at a higher data rate, which may result in increased cost, for example for EMI shielding, the codec chip transmits the data when the data is at a reduced data rate.

Abstract: A phase-locked loop circuit (“PLL”) is adjustable in both phase and frequency. By providing a plurality of taps on the voltage-controlled oscillator of the PLL, and providing separate multiplexers, each of which can select a different tap—one for the PLL feedback loop and one for the PLL output—one allows the user to adjust the phase of the output relative to that of the input. Similarly, by providing loadable pre-scale (divide by N), post-scale (divide by K) and feedback-scale (divide by M) counters, one allows the user to adjust the frequency of the output to be M/(NK) times that of the input.

Abstract: The receiver receives the standard frequency signal that includes a time code. A sampling unit samples one bit of the received signal at 32 positions. A smoothing unit smoothens the result of sampling by dividing the 32 positions in two to four intervals and determines a value of the received signal in each interval. A waveform determining unit determines waveform of each bit of the received signal based on the value obtained in the smoothing unit. The decoding unit extracts the time code based on the determined waveform. A time unit correct the time based on the extracted time code.

Abstract: A communication system includes a receiver for receiving a serial bit stream from at least one communication channel, and a decoder, in communication with the receiver, for decoding words from the received serial bit stream, the words being defined at least in part by word boundaries in the received serial bit stream. The decoder contemporaneously synchronizes detection of bits and detection of the word boundaries in the received serial bit stream. The decoder preferably decodes digitized video signal information in the serial bit stream according to a Transition Minimized Differential Signalling protocol. The receiver and decoder are preferably part of an integrated circuit chip.

Abstract: There is disclosed a technique in which any peaks above a threshold level are reduced, but not clipped, such that the effects of such peaks is reduced. Although the implementation of the technique preferably includes a clipping step, it is performed on the front-end rather than as the last step in the technique, such that the output signal is not a clipped signal. Any noise introduced by the clipping step, so-called clipping noise, is preferably filtered out of the useful frequency band of the signal.

Abstract: A system for communicating between integrated circuits is disclosed. The system includes a driver having an input and an output. In response to a logic transition from a first logic state to a second logic state at the driver input, the driver output transitions from a low-power condition, to a transmitting condition, to the low-power condition. The system also includes a receiver having an input and an output. The receiver detects the logic state of the transmitting condition at the driver output and latches it to the receiver output after the driver output returns to the low-power condition. The system also includes a transmission line, which connects the driver output to the receiver input.

Abstract: A method for reducing interference in a desired signal in a GSM communication system uses a finite-impulse-response filter for alternate linear equalization. The method includes a first step (300) of inputting a burst of data of a received waveform including interference from a channel of the communication system. A next step (302) includes training the finite-impulse-response filter with a set of symbols of specific quadrature phase, known a priori, in the burst of data of the received waveform. For example known real only and imaginary only symbols are alternatively selected from a midamble of the data burst. A next step (304) includes operating on the received waveform with the finite-impulse-response filter to alternately linearly equalize the burst of data to provide an estimate of the desired signal.

Abstract: A timing recovery circuit and related method is disclosed. The timing recovery circuit encompasses a converter, an interpolator, a phase error detector, an adjustment circuit, and a calculation circuit. The converter samples an input signal to generate an intermediate signal carrying samples of the input signal, while the interpolator inserts an interpolating sample into the intermediate signal in response to a control value to generate an output signal. The phase error detector outputs a phase error of the output signal. The adjustment circuit updates an over-sampling ratio according to a pair of first and second thresholds, and a counting value adjusted in response to the phase error and a median reference value. Finally, the calculation circuit derives the control value from the updated over-sampling ratio, and transferring the control value to the interpolator.

Abstract: Data, such as data received by a memory I/O from a memory unit in a DDR SDRAM system, is captured using a trigger signal, which may be a non free-running clock signal such as a DQS signal in a DDR SDRAM system, and is transferred to a host system, which may be part of an ASIC, using the host system's clock. The memory I/O includes a data capture register that latches the data received from the memory unit using DQS. The memory I/O also includes a FIFO buffer that latches the data output by the data capture register using a delayed version of DQS. A single edge of the delayed DQS is available to the FIFO for latching each set of data that corresponds to a single pulse of DQS. The FIFO transfers the data to the host system using the host system's clock, which represents a different clock domain than DQS.

Abstract: A data conveyance integrated system that can be utilized in a base station and/or end user devices in a wireless communication system. The integrated system includes first and second integrated circuits (ICs). The first IC includes a first serial-deserial (SERDES) module, a transmit radio frequency module, and a receive radio frequency module. The transmit and receive radio frequency modules provide the wireless communication between the base stations and end user devices. The second IC includes a second SERDES module and a programmable logic fabric programmed to implement one or more wireless communication functions. Accordingly, the programmable logic fabric generates outbound digital signals from data (e.g., video, audio, control, or text data) provided to the device, and/or processes inbound digital signals to recapture the originally transmitted data. Thus, base stations and/or end user devices within a wireless communication system can be readily reconfigured.

Abstract: A method for maintaining an accurate channel estimate. The method includes providing a reference channel estimate based on at least one long training symbol, and generating a frequency domain representation of a first data symbol including a plurality of pilots. The method then includes tracking phase change in the plurality of pilots of the first data symbol relative to pilots of the at least one long training symbol to produce correction factors, and adjusting the reference channel estimate based upon the correction factors.

Abstract: Provided is a system and method for a modem including one or more processing paths. Also included is a number of interconnected modules sequentially arrayed along the one or more paths. Each module is configured to (i) process signals passed along the paths in accordance with the sequence and (ii) implement predetermined functions to perform the processing. Further, each of the modules has a particular degree of functional programmability and the degrees of functional programmability monotonically vary in accordance with the sequence.

Abstract: The present invention provides for a method and apparatus for allocating data to subchannels used for ADSL transmission over a communication link which supports further system transmissions. An expected interference impact from the further system transmissions is estimated for the ADSL subchannels. Signal-to-noise ratios (SNRs) for the subchannels are determined for bit loading by an estimator (220). In one embodiment, actual noise associated with the communication link is used at initialization to determine a SNR which is subsequently modified by an adjusting unit (205) prior to bit loading responsive to the estimated interference impact. In another embodiment, a virtual noise signal, indicative of the estimated interference impact and generated by a noise signal generator (235), is summed with the actual noise prior to determining a SNR for bit loading.

Abstract: A system and method for synchronized communication of information between transmitting and receiving stations. The system has a first station and a second station, each attached to a modem, and a device, such as an automated link establishment controller, for establishing communications between the modems. The method involves establishing a selected communications channel between the modems and communicating data over the selected communications channel using coherent modulation synchronized by an external frequency reference without using a modem training interval.

Abstract: Transmit amplitude independent adaptive equalizers are provided that compensate for transmission losses in an input signal when the transmit signal amplitude is unknown. Several embodiments are provided, including a first embodiment having an equalizer core, a controllable-swing slicer and an amplitude control loop, a second embodiment having an equalizer core, a fixed-swing slicer and a control loop, a third embodiment having an equalizer core, a variable gain amplifier, and a variable gain amplifier control loop, and a fourth embodiment having an equalizer core, a fixed-swing slicer, a variable gain amplifier, and a variable gain amplifier control loop.

Abstract: A phase error corrector circuit and method are disclosed. In one embodiment, a phase error corrector circuit delays a PSK modulated signal and multiplies the delayed PSK modulated signal by the PSK modulated signal in order to generate a forward phase correction signal. The input signal is then mixed with the forward phase correction signal. In another embodiment, a phase error corrector circuit calculates a forward phase offset of a complex PSK modulated signal. The complex PSK modulated signal is phase shifted in a mixer by a phase difference offset in order to generate a phase corrected signal. A backward phase correction means calculates a backward phase offset based on the phase corrected signal. A subtractor subtracts the forward phase offset from the backward phase offset for outputting a difference phase offset to the mixer.

Abstract: A library is referred to and thus facilities are executed when executing an application program for receiving and transmitting radio signals. That is, the library serving as programs depending on hardware converts commands based on the application program into signal to control the hardware. As a result, the application program is describable by a program independent of an analog device for receiving and transmitting the radio signal, and a common application program can be used even in case of different hardware.