Abstract: A shift register capable of supplying only a necessary clock signal to a necessary unit register with simple constitution. A semiconductor device is provided with a shift register in which a plurality of stages of unit registers is connected, in which the unit register comprises a flip-flop circuit, a first switch and a second switch, a first clock signal line is electrically connected to the flip-flop circuit through the first switch, a second clock signal line is electrically connected to the flip-flop circuit through the second switch, the first switch is controlled to be on/off by an output signal from the flip-flop circuit, and the second switch is controlled to be on/off by an input signal to the flip-flop circuit.

Abstract: A switching control circuit of synchronous rectification type that is capable of reducing dead time is obtained. Upon detection that an output potential rises above VDD-Va, a first sensor outputs an H signal to a first input terminal of a first NOR circuit, and the first NOR circuit outputs an L signal to a second input terminal of a second NOR circuit, and the second NOR circuit outputs an H signal to a first gate driving circuit. A PMOS is thereby turned on. Upon detection that the output potential falls below GND+Vb, a second sensor outputs an L signal to a first input terminal of a first NAND circuit, and the first NAND circuit outputs an H signal to a second input terminal of a second NAND circuit, and the second NAND circuit outputs an L signal to a second gate driving circuit. An NMOS is thereby turned on.

Abstract: A multiphase clock generator circuit for generating a plurality of output clock pulses that differ in phase on the basis of a reference clock pulse, has first and second divider circuits for dividing first and second reference clock pulses that differ in phase to generate output clock pulses, and a switch for forming an intermittent short between predetermined nodes of the first and second divider circuits, wherein the switch forms a short between the predetermined nodes with timing in which the predetermined nodes are brought to the same level in a normal operating state.

Abstract: A circuit and method of correcting the duty cycle of digital signals is disclosed. The duty cycle of an input digital signal is measured and compared to a desired duty cycle. The leading edge of the input digital signal is passed to an output. The circuit and method adjust the falling edges at the output to achieve the desired duty cycle. The falling edges occur in response to rising edges of a delayed version of the input digital signal.

Abstract: Apparatus, systems, and methods implementing techniques for converting clock signals are described. A voltage-based input clock signal is received and converted into a current-based clock signal. An electrical current of the current-based clock signal is varied in response to the input clock signal while a voltage of the current-based clock signal remains substantially constant.

Abstract: A voltage redoubling circuit, wherein said circuit relies on a voltage-detecting unit, an oscillating unit, an inversing unit, a first switching device, a second switching device, a third switching device, a fourth switching device, and a fifth switching device to pump a reference voltage to an output voltage. In such a way, a conducted memory cell can be quickly and accurately accessed via a circuit operated in a low voltage region by a single on-and-off signal rather than a number of pulse control signals.

Abstract: It is an object of the present invention to improve the phase difference detection accuracy of a phase comparator. A phase difference signal generation circuit outputs a signal C_SIGNAL which takes a high level for a period corresponding to the phase difference between the comparison target signals COMP1 and COMP2 to the control terminal of a tri-state buffer, based on a signal synchronous with the start-up of the comparison target signal COMP1 detected by an edge detection flag generation circuit and a signal synchronous with the start-up of the comparison target signal COMP2 detected by an edge detection flag generation circuit. A status management circuit outputs a signal A_SIGNAL corresponding to the phase advance or delay of the comparison target signals COMP1 and COMP2 to the input terminal of the tri-state buffer.

Abstract: A power down circuit that provides an on-state electrical current to a load circuit that does not depend significantly on power control signal logic levels and that provides a widened off-state control signal voltage range. A power down circuit according to the present teachings includes a switching transistor for providing an electrical current to a load circuit in an on-state and for interrupting the electrical current in an off-state and that includes a circuit for operating the switching transistor in a triode region during the on-state.

Abstract: A resonate gate drive circuit for driving at least one power switching devices recovers energy loss for charging and discharging the input capacitance of the power switching devices. The gate drive circuit charging and discharging the gate capacitor with a high level current, so the switching loss of the power switching devices can also be reduced. The gate drive circuit can clamp and keep the voltage across the gate capacitor to a certain level while the power switching devices turn on, and it can also clamp and keep the voltage across the gate capacitor to almost zero while the power switching devices turn off. The gate drive circuit comprises four small semiconductor bidirectional conducting switching devices connected in full-bridge configuration. An inductor is connected to the two junctions of the full-bridge configuration to help switching the current direction. A capacitor in series with the inductor is necessary for some applications.

Abstract: A synchronizer system and method that can be used with a conventional adjustable delay circuit to preserve a pseudo-synchronous phase relationship between clock signals of different clock domains when the time delay of the adjustable delay circuit from which one of the clock signals is output is changed.

Abstract: A phase detection system for use with a synchronous mirror delay or a delay-locked loop in order to reduce the number of delay stages required, and therefore increase the efficiency, is disclosed. The invention includes taking a clock input signal and a clock delay or feedback signal, each having timing characteristics, and differentiating between four conditions based upon the timing characteristics of the signals. The phase detector and associated circuitry then determines, based upon the timing characteristics of the signals, which of a number of phase conditions the signals are in. Selectors select the signals to be introduced into the synchronous mirror delay or delay-locked loop by the timing characteristics of the phase conditions. The system is able to utilize the falling clock edge of the clock input signal, and the lock time is decreased under specific phase conditions.

Abstract: A resonate gate drive circuit for driving at least one power switching device recovers energy loss for charging and discharging the gate capacitance of the power switching devices. The gate drive circuit uses a current source to charge and discharge the gate capacitance with a high current, reducing the switching loss of the power switching device. The gate drive circuit comprises four semiconductor bidirectional conducting switching devices connected in a full-bridge configuration. An inductor connected across the bridge configuration provides the current source. The gate drive circuit may be used in single and dual high-side and low-side, symmetrical or complementary, power converter gate drive applications.

Abstract: A double sampled switched capacitor architecture as described herein includes an amplifier having two separate inputs corresponding to two separate amplifier sections. The amplifier uses a first differential transistor pair for the first amplifier section, a second differential transistor pair for the second amplifier section, a first tail current bias arrangement for the first differential transistor pair, and a second tail current bias arrangement for the second differential transistor pair. The tail current bias arrangements are driven by a bias switching architecture that alternately activates one tail current bias arrangement while at least partially deactivating the other tail current bias arrangement. The amplifier and bias switching architecture cooperate to eliminate gain error that would otherwise be caused by a common parasitic capacitance shared by a single amplifier section.

Abstract: A flip-flop circuit that captures an input signal in sync with a clock, has a first gate outputting a first signal corresponding with input signal; a second gate generating a second signal of a first predetermined level in response to a first level of clock and causing the second signal to be a level of first signal in response to a second level of clock; and a third gate outputting a third signal of second signal in response to the second level of clock. Further the flip-flop circuit has a first inversion feedback circuit between the third and second signal terminals, that is activated in response to the second level of clock and latches the third signal together with third gate; and level fixing circuit that fixes the first signal terminal at a second predetermined level with a time delay after the clock changes to the second level.

Abstract: An integrated circuit having cascade-connected multiplexers and a precharge unit. The cascade-connected multiplexers each have a plurality of data inputs, a data output, wherein each data input and each data output has two terminals for the application of a dual-rail signal, and a control input, wherein a signal present at the control input defines which of the data inputs is connected to the data output. The precharge unit, which is driven with a precharge unit control signal, is connected to the data output or at least one of the data inputs of one of the multiplexers to thereby bring the data outputs and/or data inputs of the multiplexers into a precharge state before execution of a computation operation.

Abstract: A comparator according to one embodiment includes first and second input terminals, first and second output terminals, first and second input inverters, first and second load inverters, and a bias control circuit to provide first and second bias voltages for application to inputs of the first and second load inverters, respectively.

Abstract: A driver circuit that prevents amplitude reduction at a high temperature comprises a differential pre-buffer circuit 22 for performing signal clamping by diodes 16 and 17 each having a nonlinear voltage-current characteristic with respect to an input signal and a differential output circuit 23 for amplifying output signals of the differential pre-buffer circuit 22, for output. The driver circuit further includes a temperature characteristic compensation circuit 44 for controlling direct currents to be passed through the diodes 16 and 17 based on a current to be passed through a diode 43 having a voltage-current characteristic with the same temperature coefficient as those of the diodes 16 and 17. A current related to constant currents I1 and I2 is supplied from the temperature characteristic compensation circuit 44 as a current that cancels the temperature characteristic of a fall in forward voltages of the diodes 16 and 17.

Abstract: A single-ended, non-differential switched capacitor circuit is disclosed which removes the effect of common mode noise. To this end, the circuit creates a capacitance divider using the sampling capacitors, Cs, to create a stable and noise-free common mode voltage (Vcom) signal. Once created, this Vcom signal is coupled across a large common mode capacitance, Ccom, which is preferably off chip, to further control its value. Thereafter, the voltage Vcom is preferably allowed to settle while the data is disconnected. In this way, the Vcom signal is not provided to the circuit, but instead is cleanly generated within the circuit itself when needed. Thereafter, the generated Vcom signal is paralleled with the integration capacitor, C1, to produce the non-differential output voltage Vout. Then, the sampling capacitors, Cs, are shorted to remove any charges stored on them and the process is repeated.

Abstract: A double sampled switched capacitor architecture as described herein includes an amplifier having two separate inputs corresponding to two separate amplifier sections. The amplifier uses a first differential transistor pair for the first amplifier section, a second differential transistor pair for the second amplifier section, a first tail current bias arrangement for the first differential transistor pair, and a second tail current bias arrangement for the second differential transistor pair. The tail current bias arrangements are driven by a bias switching architecture that alternately activates one tail current bias arrangement while at least partially deactivating the other tail current bias arrangement. The amplifier and bias switching architecture cooperate to eliminate gain error that would otherwise be caused by a common parasitic capacitance shared by a single amplifier section.

Abstract: A high voltage gate driver circuit according to an embodiment of the present invention controls an operational range of an output signal of a level shifter to be appropriate for an operational range of a reshaper through a VIV converter. Even though the voltage range of the signal which is input from the high voltage gate driver circuit to the level shifter is different from the operational range of the reshaper, the input signal can always be recognized exactly regardless of the VTH voltage of the reshaper by controlling the operational range of the signal through the VIV converter. In addition, incorrect operation of the circuit can be prevented by erasing a common mode noise which is input with the input signal.