Patents Examined by Khareem E. Almo
  • Patent number: 11128496
    Abstract: A transmitter with low power and high accuracy equalization is shown. The transmitter includes a transmitter driver and a driver bias circuit. The transmitter driver receives data, and generates a positive differential output and a negative differential output to be transmitted by the transmitter. The driver bias circuit is coupled to the transmitter driver to bias the transmitter driver, wherein the driver bias circuit is configured to boost the bias level of the transmitter driver in response to transitions of the data.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: September 21, 2021
    Assignee: MEDIATEK INC.
    Inventor: Hung-Yi Hsieh
  • Patent number: 11121624
    Abstract: A configurable multi-output charge pump for power supply generation includes one or more flying capacitors (FCs) arranged to be switchably connected into a plurality of circuit configurations operative to provide respective output voltages at a common charging node. A configuration logic circuit is operative to generate one or more configuration setting control signals to effectuate a particular circuit configuration. One or more storage capacitors (SC) are independently and individually connectable to the common charging node depending on a selection control logic having a configurable duty cycle, wherein each SC is operative to supply a respective voltage output to drive a corresponding electrical load.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: September 14, 2021
    Assignee: Advanced Neuromodulation Systems, Inc.
    Inventor: Daran DeShazo
  • Patent number: 11115244
    Abstract: A signal isolator integrated circuit package includes a first circuit having a first input and a first output, a second circuit having a second input and a second output, an isolation barrier layer between the first circuit and the second circuit, wherein the second output of the second circuit is coupled to the first input of the first circuit through the isolation barrier. The signal isolator includes a comparator configured to compare the first input of the first circuit to the second output of the second circuit. The second output can be configured to convey at least three states, including a first state indicative of a logical high of an input signal received at the first input, a second state indicative of a logical low of the input signal, and a third state indicative of a fault condition.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: September 7, 2021
    Assignee: Allegro MicroSystems, LLC
    Inventors: Robert A. Briano, Pedram Sotoodeh Shahnani, Cory Voisine
  • Patent number: 11115010
    Abstract: A dielectric structure is loaded with energy (e.g., charge), which is retained therein until a trigger causes rapid discharge of the loaded energy and generation of an accompanying electromagnetic pulse (EMP). By appropriate design of the dielectric structure and/or trigger, the waveform of the EMP resulting from the rapid discharge can be tailored. Features of the dielectric structure can be modified and/or other devices can be coupled to the dielectric structure to also tailor the EMP, for example, to provide directionality. A modeling unit can predict the discharge in the dielectric structure and/or resulting EMP. The modeling unit can be used to determine charge density spatial distribution within the dielectric structure, shape of the dielectric structure, and/or actuation timing/location necessary to yield a desired waveform for the EMP emanating from the dielectric structure upon discharge.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: September 7, 2021
    Inventors: Timothy W. Koeth, George Hine
  • Patent number: 11115015
    Abstract: A circuit component has an address determined from a voltage level applied to a single electrical contact of the circuit component. The circuit component is configured to be assigned one of at least three unique addresses and to select from among the at least three unique addresses based on the voltage level.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: September 7, 2021
    Inventors: Bo Zhou, Guillaume Alexandre Blin
  • Patent number: 11096673
    Abstract: A transmit signal generator is provided. The transmit signal generator has an n?1 bit comparator having a first set of n?1 input lines and a second set of n?1 input lines and an output line, the n?1 bit comparator operable to compare signals of the first set of n?1 input lines and signals of the second set of n?1 input lines and provide the output of the n?1 bit comparator based on the comparison, and an n-bit binary counter having a clock signal input line, a reset signal input line, a clock enable line connected to the output line of the n?1 bit comparator, and n output lines. One of the n output lines provides a sequence of pulse as an output of the transmit signal generator.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: August 24, 2021
    Assignee: MTEC GLOBAL CO., LTD.
    Inventor: Kyusun Choi
  • Patent number: 11101789
    Abstract: A bi-directional level shift circuit shifts signal levels between a first signal line and a second signal line. The circuit includes a first transistor and a second transistor. The first transistor includes a first gate connected to the second signal line, a first source connected to the first signal line, and a first drain connected to a voltage rail which supplies voltage. The second transistor includes a second gate connected to the voltage rail, a second source connected to the first signal line, and a second drain connected to the second signal line.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: August 24, 2021
    Inventors: Paul V. Mullins, Jr., Gabriel J. Kuenn
  • Patent number: 11095277
    Abstract: A voltage source device includes a voltage converter configured to generate a supply voltage at an output node of the voltage converter. A current source is configured to apply a current to a first output terminal of the voltage source device in order to detect a cable voltage drop. A compensation circuit is configured to generate a feedback signal based on a voltage at the first output terminal. The supply voltage is generated based on the feedback signal.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: August 17, 2021
    Inventors: Alexandre Pons, Jean Camiolo
  • Patent number: 11088680
    Abstract: Methods and apparatus for reducing Miller effect in SiC MOSFETs are provided. An example apparatus includes a plurality of SiC MOSFETs and a Miller current cancellation circuit configured to mitigate Miller current induced by switching transients associated with the plurality of SiC MOSFETS. The Miller current cancellation circuit includes a two-stage voltage sampling circuit configured to sample a drain to source voltage of a SiC MOSFET of the plurality of SiC MOSFETs, a voltage inverting circuit configured to invert the sampled drain to source voltage, and an injection capacitor configured to generate, by way of receiving the inverted sampled drain to source voltage as input, inverse Miller current to mitigate the Miller current within the plurality of SiC MOSFETS.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: August 10, 2021
    Assignee: University of Florida Research Foundation, Incorporated
    Inventors: Shuo Wang, Boyi Zhang
  • Patent number: 11070091
    Abstract: In a wireless power transfer system for supplying power to a wireless device, e.g., charging a battery, wireless power transmitter coil voltage is used in place of coil current for communication and power control reference. The transmitter coil voltage waveforms provide phase information, with reference to the pulse width modulation (PWM) waveforms, that can be used to demodulate digital packet communication from a wireless power receiver used to provide a voltage to a device. The DC voltage amplitude of the wireless power transmitter coil is used for controlling the power injected to the wireless power receiver coil, while the phase of the transmitter coil voltage PWM signal is used for demodulation of signal packets from the wireless power receiver to control the transmitter coil voltage and thereby wireless power transfer to the power receiver.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: July 20, 2021
    Inventors: Santosh Manjunath Bhandarkar, Alex Dumais
  • Patent number: 11069477
    Abstract: A coil unit capable of inhibiting overheating in a magnetic body while the amount of the magnetic body used is reduced includes a magnetic body and a coil with an opening, the magnetic body overlaps the coil in a first direction and includes first, second, and third areas, the first area includes first and second faces, the second area includes third and fourth faces, the third area includes fifth and sixth faces, a first distance between the fifth face and the coil is shorter than a second distance between the second face and the coil and is longer than a third distance between the first face and the coil, a fourth distance between the third face and the coil is shorter than the first distance, and a fifth distance between the fourth face and the coil is longer than the third distance.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: July 20, 2021
    Inventor: Akihiro Ii
  • Patent number: 11070205
    Abstract: When a signal glitches, logic receiving the signal may change in response, thereby charging and/or discharging nodes within the logic and dissipating power. Providing a glitch-free signal may reduce the number of times the nodes are charged and/or discharged, thereby reducing the power dissipation. A technique for eliminating glitches in a signal is to insert a storage element that samples the signal after it is done changing to produce a glitch-free output signal. The storage element is enabled by a “ready” signal having a delay that matches the delay of circuitry generating the signal. The technique prevents the output signal from changing until the final value of the signal is achieved. The output signal changes only once, typically reducing the number of times nodes in the logic receiving the signal are charged and/or discharged so that power dissipation is also reduced.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: July 20, 2021
    Assignee: NVIDIA Corporation
    Inventor: William James Dally
  • Patent number: 11063597
    Abstract: Described is a delay-locked loop which includes a frontend circuit configured to output a control voltage based on an input clock and a feedback clock and a delay line circuit connected to the frontend circuit. The delay line circuit configured to generate a bias voltage based on the control voltage and a step size, where the bias voltage is variable based on the step size, and apply at least one level of delay on the input clock based on the bias voltage to generate an output clock, where the feedback clock being based on the output clock and where the input clock is aligned with the feedback clock by delaying the phase of the output clock until phase lock.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: July 13, 2021
    Assignee: SiFive, Inc.
    Inventors: Santosh Mahadeo Narawade, Jithin K, Mohit Gupta
  • Patent number: 11063582
    Abstract: A current detection circuit includes normally-on-type and a first normally-off-type switching elements with main current paths that are connected in series, and a second normally-off-type switching element that has a source and a gate that are connected to a source and a gate of the first normally-off-type switching element and a drain that is connected to a constant current source, and executes a division process by using drain voltages of the two normally-off-type switching elements.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: July 13, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Hideaki Majima
  • Patent number: 11056925
    Abstract: An object of the present invention is to reduce the possibility of failure in the detection of metallic foreign object. A metallic foreign object detector includes a sensor part having at least one antenna coil that receives a magnetic field or current to generate a vibration signal a vibration time length measurement circuit that measures a vibration time length indicating the length of time required for the vibration of the vibration signal output from the sensor part corresponding to a predetermined wavenumber larger than 1, and a determination circuit that determines the presence/absence of a metallic foreign object approaching the antenna coil based on the vibration time length and a criterion vibration time length which is the vibration time length obtained in the absence of the approaching metallic foreign object.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: July 6, 2021
    Inventors: Kazuki Kondo, Kazunori Oshima, Akira Gotani, Narutoshi Fukuzawa
  • Patent number: 11057029
    Abstract: A gate driver with an integrated Miller clamp controls a high-power drive device coupled to a terminal of a package that houses an integrated circuit coupled to the terminal. A method includes generating an indication of a level of a signal on the terminal with respect to a predetermined signal level. The method includes configuring a variable strength driver of the integrated circuit to charge, discharge, or clamp the terminal based on a control signal and the indication.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: July 6, 2021
    Assignee: Silicon Laboratories Inc.
    Inventors: Alan L. Westwick, Peter Onody, András V. Horváth, Tamás Marozsák
  • Patent number: 11052771
    Abstract: Provided is a vehicle-mounted power supply device detecting connection with an external power source and charging a power storage unit by stepping up a supply voltage based on the external power source. A vehicle-mounted power supply device includes an external terminal to which a power supply path from an external power source is connectable, a detection unit detects that the power supply path is connected to the external terminal, and a power supply circuit unit allows for flow of a current from the external terminal side toward the second conduction path side at least when the power supply path is connected to the external terminal. The control unit controls a step-down operation and a step-up operation of the voltage conversion unit, and causes the voltage conversion unit to perform the step-up operation when connection between the external terminal and the power supply path is detected by the detection unit.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: July 6, 2021
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Takanori Itou, Seiji Takahashi
  • Patent number: 11050416
    Abstract: Implementation of large temperature-insensitive resistance in CMOS using short-duty-clock cycle is provided herein. Operations of a method can comprise boosting a resistance level of a switched-resistor circuit to a defined resistance level. The boosting can comprise using a short-duty-cycle clock to facilitate the boosting. Also provided is a sensor system that can comprise a short-duty-cycle clock and a switched-resistor circuit. The short-duty cycle clock boosts a resistance level of the switched-resistor circuit to a defined resistance level.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: June 29, 2021
    Assignee: INVENSENSE, INC.
    Inventors: Jialin Liu, Ming He, Richelle Smith
  • Patent number: 11025062
    Abstract: Apparatus for use in a microgrid, which comprises a DC bus with at least one DC power source connected thereto, an AC bus connected to a mains power grid that supplies the microgrid, and a DC/AC converter coupling the DC bus and the AC bus, wherein the DC/AC converter may be a one-way DC/AC inverter or a bidirectional DC/AC converter, the apparatus comprising a control system, which is configured to control number (at least one) DC power converters, each of which is configured to couple a respective controllable DC load to the DC bus, and to control the power flowing from the DC bus to each of the number controllable DC loads, so as to control each of the number controllable DC loads to fulfil its function and the voltage on the DC bus.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: June 1, 2021
    Inventor: Xiongwei Liu
  • Patent number: 11025241
    Abstract: A comparator circuit includes a differential input circuit, a load circuit, a first current source, a first bias voltage supplying circuit, a third connection circuit, and a fourth connection circuit. The differential input circuit includes a first transistor to which a first input signal is supplied and a second transistor to which a second input signal is supplied. The load circuit includes a third transistor connected to the first transistor through a first connection circuit and a fourth transistor connected to the second transistor through a second connection circuit, gates of the third and fourth transistors being connected to the first connection circuit through a third capacitor. The first bias voltage supplying circuit supplies a first bias voltage to the gates of the third and fourth transistors and the third capacitor.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: June 1, 2021
    Inventors: Shinji Nakatsuka, Koji Mishina, Noriyuki Fukushima