Patents Examined by Kiesha L. Rose
  • Patent number: 7692212
    Abstract: A double heterojunction bipolar transistor on a substrate comprises a collector formed of InGaAsP, a base in contact with the collector, an emitter in contact with the base, and electrodes forming separate electrical contacts with each of the collector, base, and emitter, respectively. A device incorporates this transistor and an opto-electronic device optically coupled with the collector of the transistor to interact with light transmitted therethrough.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: April 6, 2010
    Assignee: HRL Laboratories, LLC
    Inventors: Rajesh D. Rajavel, Stephen Thomas, III
  • Patent number: 7674656
    Abstract: A method that locates a plurality of die for forming a plurality of packaged integrated circuits. A frame is placed over the support structure, wherein the frame includes a plurality of openings therein and each opening of the plurality of openings has at least two walls. Each die of a plurality of die is placed over the support structure, wherein each die has at least two adjacent edges. The relative placing of the frame and the die results in each die being in an opening of the plurality of openings. Encapsulant is applied to the plurality of die. Either or both of the plurality of die and frame are moved in relation to the other in a manner that causes the two adjacent edges of each die of the plurality of die to substantially abut to and align with the two walls of an opening of the plurality of openings.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: March 9, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert J. Wenzel, Matthew A. Ruston, David M. Wells
  • Patent number: 7659137
    Abstract: A fabrication method of fabricating a structure capable of being used for generation or detection of electromagnetic radiation includes a forming step of forming a layer containing a compound semiconductor on a substrate at a substrate temperature below about 300° C., a first heating step of heating the substrate with the layer in an ambience containing arsenic, and a second heating step of heating the substrate with the layer at the substrate temperature above about 600° C. in a gas ambience incapable of chemically reacting on the compound semiconductor. Structures of the present invention capable of being used for generation or detection of electromagnetic radiation can be fabricated using the fabrication method by appropriately regulating the substrate temperature, the heating time, the gas ambience and the like in the second heating step.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: February 9, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shintaro Kasai, Toshihiko Ouchi, Masatoshi Watanabe, Mitsuru Ohtsuka, Taihei Mukaide
  • Patent number: 7655987
    Abstract: A metal-oxide-semiconductor (MOS) transistor device is disclosed. The MOS transistor device comprises a semiconductor substrate; a gate structure on the semiconductor substrate; source/drain regions on the semiconductor substrate adjacent to the gate structure; an ultra-high tensile-stressed nitride film having a hydrogen concentration of less than 1E22 atoms/cm3 covering the gate structure and the source/drain regions; and an inter-layer dielectric (ILD) film over the ultra-high tensile-stressed nitride film.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: February 2, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Neng-Kuo Chen, Teng-Chun Tsai, Chien-Chung Huang, Tsai-Fu Chen, Wen-Han Hung
  • Patent number: 7652378
    Abstract: A semiconductor metal structure with an efficient usage of the chip area is provided. The structure includes a substrate, a copper-based interconnection structure over the substrate, the copper-based interconnection structure comprising a plurality of metallization layers connected by vias and in first dielectric layers, at least one aluminum-based layer over and connected to the copper-based interconnection structure, wherein a top layer of the at least one aluminum-based layer comprises a bond pad and an interconnect line connecting to two underlying vias, vias/contacts connecting a top layer of the copper-based interconnection structure and a bottom layer of the at least one aluminum-based layer, wherein the vias/contacts are in a second dielectric layer, and a third dielectric layer overlying the at least one aluminum-based layer, wherein the bond pad is exposed through an opening in the third dielectric layer.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: January 26, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Horng-Huei Tseng, Chenming Hu
  • Patent number: 7645641
    Abstract: An integrated circuit package includes: a substrate; an electronic circuit located on the substrate, the electronic circuit comprising a topography of at least one level; a cooling device located over the electronic circuit; a compliant interface disposed between the electronic circuit and the cooling device, wherein the compliant interface comprises a first surface and a second surface and wherein the first surface is in thermal contact with the electronic circuit, and wherein the compliant interface is preformed from a compliant material such that the first surface substantially conforms to the topography of the electronic circuit.
    Type: Grant
    Filed: July 23, 2007
    Date of Patent: January 12, 2010
    Assignee: International Business Machines Corporation
    Inventor: Bucknell C Webb
  • Patent number: 7646075
    Abstract: Microelectronic imager assemblies with front side contacts and methods for fabricating such microelectronic imager assemblies are disclosed herein. In one embodiment, a microelectronic imager assembly comprises a workpiece including a substrate having a front side and a backside. The assembly further includes a plurality of imaging dies on and/or in the substrate. The imaging dies include image sensors at the front side of the substrate, integrated circuitry operatively coupled to the image sensors, and bond-pads at the front side of the substrate electrically coupled to the integrated circuitry. The assembly also includes a plurality of stand-offs at the front side of the substrate. The stand-offs have apertures aligned with corresponding image sensors. The assembly further includes a plurality of external contacts electrically coupled to corresponding bond-pads and projecting away from the dies.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: January 12, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Salman Akram
  • Patent number: 7646055
    Abstract: A method includes the steps of: introducing insulation film into a trench to provide a trench isolation; planarizing the trench isolation to expose a passivation film; and removing the passivation film and depositing a second silicon layer on a first silicon layer and the trench isolation; and in the step of depositing the first silicon layer the first silicon layer is an undoped silicon layer and in the step of depositing the second silicon layer the second silicon layer is a doped silicon layer or an undoped silicon layer subsequently having an impurity introduced thereinto or the like and thermally diffused through subsequent thermal hysteresis into the first silicon layer.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: January 12, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yasuki Morino, Yoshihiko Kusakabe, Ryuichi Wakahara
  • Patent number: 7645687
    Abstract: An embodiment of fabrication of a variable work function gates in a FUSI device is described. The embodiment uses a work function doping implant to dope the polysilicon to achieve a desired work function. Selective epitaxy growth (SEG) is used to form silicon over the source/drain regions. The doped poly-Si gate is fully silicided to form fully silicided gates that have a desired work function. We provide a substrate having a NMOS region and a PMOS region. We form a gate dielectric layer and a gate layer over said substrate. We perform a (gate Vt) gate layer implant process to implant impurities such as P+, As+, B+, BF2+, N+, Sb+, In+, C+, Si+, Ge+ or Ar+ into the gate layer gate in the NMOS gate regions and said PMOS gate regions. We form a cap layer over said gate layer. We pattern said cap layer, said gate layer and said gate dielectric layer to form a NMOS gate and a PMOS gate. Spacers are formed and S/D regions are formed. A metal is deposited over said substrate surface.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: January 12, 2010
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Yung Fu Chong, Dong Kyun Sohn, Chew-Hue Ang, Purakh Raj Vermo, Liang Choo Hsia
  • Patent number: 7645620
    Abstract: A method for reducing edge effect interference with critical dimension (CD) measurement of semiconductor via structures includes forming a test structure in a kerf region of a semiconductor wafer, the test structure including at least a via structure and a trench structure in contact with the via structure. The via structure is formed in accordance with a critical dimension associated with a corresponding via structure in a circuit region of the semiconductor wafer, and the trench structure is formed in accordance with a widened dimension with respect to a minimum ground rule dimension associated with a corresponding trench structure in a circuit region of the semiconductor wafer.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: January 12, 2010
    Assignee: International Business Machines Corporation
    Inventors: Alexander L. Martin, Eric P. Solecky
  • Patent number: 7646096
    Abstract: A semiconductor device having good production stability and excellent in a contact property between an antireflection film on an Al contained metal film and a conductive plug. The device includes a substrate, an insulating interlayer, and a multi-layer structure. The insulating interlayer is formed in the upper portion of the substrate. The structure is provided on the insulating interlayer. A Ti film, a first TiN film, an AlCu film, a Ti film, a second TiN film, and an etching adjustment film are sequentially formed in the structure. The device includes an insulating interlayer and a conductive plug. The insulating interlayer is provided on the insulating interlayer and the structure. The conductive plug penetrates the insulating interlayer and the etching adjustment film, and an end surface of the conductive plug is located in the second TiN film. The conductive plug includes a Ti film, a TiN film, and a W film.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: January 12, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Masashige Moritoki, Kouichi Konishi
  • Patent number: 7642560
    Abstract: A composite semiconductor light-emitting device includes a first semiconductor element portion made of a first semiconductor material and a second semiconductor element portion made of a second semiconductor material different from the first semiconductor material. The first semiconductor element portion has a first semiconductor layered structure, and the second semiconductor element portion has a second semiconductor layered structure. The first semiconductor element portion has a plurality of light-emitting regions that emit lights of different wavelengths. The second semiconductor element portion has at least one light-emitting region that emits light whose wavelength is different from the lights emitted by the light-emitting regions of the first semiconductor element portion. The light-emitting regions of the first semiconductor element portion and at least one light-emitting region of the second semiconductor element portion are electrically connected to each other.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: January 5, 2010
    Assignee: Oki Data Corporation
    Inventor: Mitsuhiko Ogihara
  • Patent number: 7642556
    Abstract: A compound semiconductor element is provided which electrically connects an electrode 3 formed on one main surface 2a of a compound semiconductor region 2 with a substrate 5 to fix an electric potential of substrate 5 at an electric potential of electrode 3, thereby preventing fluctuation in electric potential of substrate 5 under the changing operating condition of the device for stabilization in electric property of the device. Also, formed between compound semiconductor region 2 and substrate 5 is an insulating layer 6 for blocking a leakage current which may flow longitudinally between one main surface 2a of compound semiconductor region 2 and substrate 5 so that sufficiently high withstand voltage property can be given between compound semiconductor region 2 and substrate 5.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: January 5, 2010
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Shinichi Iwakami
  • Patent number: 7642125
    Abstract: An array of “mushroom” style phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming an isolation layer on the separation layer and forming an array of memory element openings in the isolation layer using a lithographic process. Etch masks are formed within the memory element openings by a process that compensates for variation in the size of the memory element openings that results from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings. Electrode material is deposited within the electrode openings; and memory elements are formed within the memory element openings. The memory elements and bottom electrodes are self-aligned.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: January 5, 2010
    Assignees: Macronix International Co., Ltd., International Business Machines Corporation
    Inventors: Hsiang-Lan Lung, Chung Hon Lam
  • Patent number: 7638351
    Abstract: A photodiode and a method of fabricating a photodiode for reducing modal dispersion and increasing travel distance. The central region of the photodiode is made less responsive to incident light than a peripheral region of the photodiode. The less responsive central region discriminates the lower order modes such that only the higher order modes are incident on the more responsive peripheral region. Because the lower order modes are subtracted, the range of propagation constants is reduced and modal dispersion is also reduced.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: December 29, 2009
    Assignee: Finisar Corporation
    Inventor: Jimmy A. Tatum
  • Patent number: 7638437
    Abstract: Provided is an in-situ thin-film deposition method in which a TiSix/Ti layer or TiSix/Ti/TiN layer can be continuously deposited. The method serves to deposit a thin layer as a resistive contact and barrier on a loaded wafer and is performed in a thin-film deposition apparatus including a transfer chamber having a robot arm therein and a plurality of chambers installed as a cluster type on the transfer chamber. The method includes depositing a TiSix layer on the wafer by supplying a first reactive gas containing Ti and a second reactive gas containing Si to a first chamber; and transferring the wafer to a second chamber using the transfer chamber and depositing a TiN layer on the TiSix layer.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: December 29, 2009
    Assignee: IPS Ltd.
    Inventors: Tae Wook Seo, Young Hoon Park
  • Patent number: 7638809
    Abstract: A light emitting device includes a transparent substrate having first and second surfaces, a semiconductor layer provided on the first surface, a first light emission layer provided on the semiconductor layer and emitting first ultraviolet light including a wavelength corresponding to an energy larger than a forbidden bandwidth of a semiconductor of the semiconductor layer, a second light emission layer provided between the first light emission layer and the semiconductor layer, absorbing the first ultraviolet light emitted from the first light emission layer, and emitting second ultraviolet light including a wavelength corresponding to an energy smaller than the forbidden bandwidth of the semiconductor of the semiconductor layer, and first and second electrodes provided to apply electric power to the first light emission layer.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: December 29, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasuo Ohba
  • Patent number: 7635599
    Abstract: Three terminal magnetic sensing devices (TTMs) having base lead layers in-plane with collector substrate materials, and methods of making the same, are disclosed. In one illustrative example, a collector substrate having an elevated region and a recessed region adjacent the elevated region is provided. An insulator layer is formed in full-film over the collector substrate, and a base lead layer is formed in full-film over the insulator layer and in-plane with semiconductor materials of the elevated region. The insulator materials and the base lead materials that are formed over the elevated region are removed. A sensor stack structure having an emitter region and a base region is then formed over the elevated region such that part of the base region is formed over an end of the base lead layer. A base conductive via may be formed to contact base lead materials of the base lead layer at a suitable distance away from the sensor stack structure.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: December 22, 2009
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Robert E. Fontana, Jr., Jui-Lung Li, Jeffrey S. Lille, Sergio Nicoletti
  • Patent number: 7635866
    Abstract: Protrusions called ridges are formed on the surface of a crystalline semiconductor film formed by a laser crystallization method or the like. A heat absorbing layer are formed below a semiconductor film. When the semiconductor film is crystallized by laser, a temperature difference is produced between a semiconductor film 1010 positioned above a heat absorbing layer 1011 and a semiconductor film 1013 of the other region to produce a difference in thermal expansion at the boundary of the outside end 1015 of the heat absorbing layer. This difference produces a strain to form a surface wave. The surface wave starting at the outer periphery of the heat absorbing layer is formed in the vicinity of the heat absorbing layer. When the semiconductor layer is solidified after it is melted, the protrusions of the surface wave remain as protrusions after the semiconductor film is solidified.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: December 22, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Setsuo Nakajima, Ritsuko Kawasaki
  • Patent number: 7633086
    Abstract: A light emitting device is disclosed which includes a substrate, a plurality of anode electrode layers disposed in a first direction on the substrate, a plurality of cathode electrode layers disposed in a second direction different from the first direction on the substrate, a plurality of data lines electrically communicated with the anode electrode layers, and a plurality of scan lines electrically communicated with the cathode electrode layers.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: December 15, 2009
    Assignee: LG Display Co., Ltd.
    Inventor: Chun Tak Lee