Abstract: The present invention provides a non-volatile switching element having a novel structure that operates at a high speed and enables high integration, and an integrated circuit that includes such non-volatile switching elements. The switching element includes: a switching film formed on a substrate, made of a material causing a 10 times or greater change in electric resistance with a temperature change within a range of ±80 K from a predetermined temperature; a Peltier element causing the switching film to have the temperature change; a heat conducting/electric insulating film provided between the switching film and the Peltier element, to conduct heat from the Peltier element; and a pair of electrodes connected to the switching film.

Abstract: A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are formed. Thus, it may be possible to reduce the likelihood of an undesirable connection between an interconnection layer connected to the source and drain regions and a lower sidewall of the active region so that charge leakage from the interconnection layer to a substrate can be prevented or reduced. The sidewall protection layer may be formed using the device isolation layer. Alternatively, an insulating layer having an etch selectivity with respect to an interlayer insulating layer may be formed on the device isolation layer so as to cover the sidewall of the active region.

Abstract: A metal-insulator-metal (MIM) capacitor that includes a silicon nitride (SiN) dielectric film is disclosed. The MIM capacitor includes a bottom electrode, a top electrode and a dielectric layer positioned between the bottom electrode and the top electrode. The dielectric layer includes a silicon nitride film that has a plurality of silicon-hydrogen bonds and a plurality of nitride-hydrogen bonds. A ratio of silicon-hydrogen bonds to nitride-hydrogen bonds is equal to or smaller than 0.5. Accordingly, the nitrogen-rich and compressive silicon nitride film can improve the breakdown voltage of the MIM capacitor.

Abstract: The invention provides methods for reducing trap densities at interfaces in a multilayer semiconductor wafer, specifically trap densities between an active layer and an insulating layer under the active layer. The methods comprise exposing wafers to high temperatures in a generally neutral atmosphere that also comprises one or more species that can, or whose ions can, migrate into the wafer down to the interface where reduction of the trap density is desired.

Abstract: Semiconductor memory array and process of fabrication in which a plurality of bit line diffusions are formed in a substrate, and memory cells formed in pairs between the bit line diffusions, with each of the pairs of cells having first and second conductors adjacent to the bit line diffusions, floating gates beside the first and second conductors, an erase gate between the floating gates, and a source line diffusion in the substrate beneath the erase gate, and at least one additional conductor capacitively coupled to the floating gates. In some disclosed embodiments, the conductors adjacent to the bit line diffusions are word lines, and the additional conductors consist of either a pair of coupling gates which are coupled to respective ones of the floating gates or a single coupling gate which is coupled to both of the floating gates.

Abstract: The invention concerns a transparent light-emitting component, in particular an organic light-emitting diode (OLED), with a layer arrangement in which a light-emitting organic layer is arranged between an upper and a lower electrode, the layer arrangement being transparent in a switched-off state and emitting light which is produced in the light-emitting organic layer by applying an electric voltage to the upper and the lower electrode in a switched-on state, which light is radiated in a ratio of at least approximately 4:1 through the upper or the lower electrode and where a stack, which is transparent in the visible spectral region, of dielectric layers is arranged on the side of the upper or the lower electrode.

Abstract: A non-volatile memory device including a barrier spacer that serves to protect a control gate, including a metal layer, from damage that may result from exposure to a cleaning solution and/or oxygen. With the barrier spacer layer, a cleaning process using a high-power cleaning solution may be used to effectively remove etch byproducts. An oxidation process may be performed to cure etch damage of an intergate dielectric pattern, a floating gate and a gate insulator. The barrier spacer and/or the oxidation process enable a non-volatile memory device having enhanced speed and reliability to be formed.

Abstract: A photo detector is disclosed. The photo detector has a substrate, a semiconductor layer disposed on the substrate, an insulating layer covered on the semiconductor layer, an interlayer dielectric layer covered on the insulating layer, and two electrodes formed on a portion of the interlayer dielectric layer. The semiconductor layer has a first doping region, a second doping region, and an intrinsic region located between the first doping region and the second doping region. The interlayer dielectric layer has at least three holes to expose a portion of the insulating layer, a portion of the first doping region, and the second doping region. The electrodes are connected to the first doping region and the second doping region through two of the holes.

Abstract: A magnetic memory device comprising, a magneto-resistance effect element that is provided at an intersection between a first write line and a second write line. And the magneto-resistance effect element having, an easy axis that extends in a direction of extension of the first write line, and a first conductive layer for electrical connection to the magneto-resistance effect element, the first conductive layer having sides which are in flush with sides of the magneto-resistance effect element.

Abstract: A semiconductor device having a substrate that contains an insulating layer and a semiconductor layer provided on the insulating layer. The semiconductor also has an optical waveguide that is formed along a predetermined path. This optical waveguide is formed by making the semiconductor layer non-uniformed in thickness thereof. The semiconductor further has a photoreceptor having MISFET containing a floating channel body that is formed on a position of the semiconductor layer in which electric field of light guided inside the optical waveguide exists and a gate for forming channel formed on a front surface side of the channel body.

Abstract: The present invention provides an insulated gate semiconductor device which has floating regions around the bottoms of trenches and which is capable of reliably achieving a high withstand voltage. An insulated gate semiconductor device 100 includes a cell area through which current flows and an terminal area which surrounds the cell area. The semiconductor device 100 also has a plurality of gate trenches 21 in the cell area and a plurality of terminal trenches 62 in the terminal area. The gate trenches 21 are formed in a striped shape, and the terminal trenches 62 are formed concentrically. In the semiconductor device 100, the gate trenches 21 and the terminal trenches 62 are positioned in a manner that spacings between the ends of the gate trenches 21 and the side of the terminal trench 62 are uniform. That is, the length of the gate trenches 21 is adjusted according to the curvature of the corners of the terminal trench 62.

Abstract: This invention provides a circuit structure with a double-gate organic thin film transistor device and application thereof. A protection layer covered on an organic thin film transistor structure having a bottom gate is used as another gate insulating layer. A metal layer is formed on this gate insulating layer to serve as another gate. A double-gate structure is hence accomplished. The double-gate structure can be used in a circuit. By the double-gate structure the threshold voltage of the organic thin film transistor can be adjusted, and advantageously changing the characteristic of the organic thin film transistor to improve the accuracy of signal transmission.

Abstract: A power semiconductor device that includes a plurality of source trenches that extend to a depth below the gate electrodes and a termination region that includes a termination trench that is as deep as the source trenches.

Abstract: An interconnect structure having improved electromigration (EM) reliability is provided. The inventive interconnect structure avoids a circuit dead opening that is caused by EM failure by incorporating a EM preventing liner at least partially within a metal interconnect. In one embodiment, a “U-shaped” EM preventing liner is provided that abuts a diffusion barrier that separates conductive material from the dielectric material. In another embodiment, a space is located between the “U-shaped” EM preventing liner and the diffusion barrier. In yet another embodiment, a horizontal EM liner that abuts the diffusion barrier is provided. In yet a further embodiment, a space exists between the horizontal EM liner and the diffusion barrier.

Abstract: A method of manufacturing a semiconductor light-emitting device comprises selectively etching a semiconductor layer structure (16) fabricated in a nitride materials system and including an aluminum-containing cladding region or an aluminum-containing optical guiding region (5). The etching step forms a mesa (17), and also exposes one or more portions of the aluminum-containing cladding region or the aluminum-containing optical guiding region (5). The or each exposed portion of the aluminum-containing cladding region or the aluminum-containing optical guiding region (5) is then oxidized to form a current blocking layer (18) laterally adjacent to and extending laterally from the mesa. When an electrically conductive contact layer (11) is deposited, the current blocking layer (18) will prevent the contact layer (11) from making direct contact with the buffer layer (3).

Abstract: A method for manufacturing a semiconductor device includes the steps of forming an interconnection layer including a top tungsten layer, forming a mask pattern on the tungsten layer, nitriding a portion of the tungsten layer in a plasma nitriding process to form a tungsten nitride layer, etching the tungsten nitride layer while leaving the mask pattern on the tungsten layer, and patterning the interconnection layer by using the mask pattern as an etching mask.

Abstract: The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.

Abstract: A vertical organic transistor is disclosed, which includes at least: a collector contact layer disposed on a substrate; a first organic semiconductor layer disposed on the collector contact layer; a base contact layer disposed on the first organic semiconductor layer, wherein the base contact layer comprises no less than two layers of hetero-metal layers or hetero-conductive organic layers; a second organic semiconductor layer disposed on the base contact layer; and an emitter contact layer disposed on the second organic semiconductor layer. Device properties such as output current and Ion/Ioff rate can be improved by using the vertical organic transistor of this invention.

Abstract: A power converter includes a switch controller generating a pulse signal controlling a switch to emulate peak current mode control. The switch controller generates a control voltage from a representation of an output voltage of the power converter and a reference voltage. Based on the control voltage and a representation of an input voltage of the power converter, the switch controller determines a peak current in that switching cycle. If the peak current detected exceeds a maximum peak current, an on-time of the pulse signal in the next switching cycle is decreased. The power converter also provides short circuit or overload protection by increasing an off-time of the pulse signal until the off-time exceeds a transformer reset time of a transformer. If the switch period increased to prevent short circuit or overload exceeds a limit, the pulse signal is shut off immediately.

Abstract: An integrated heat spreader and die coupled with solder are disclosed herein. The heat spreader may have solder reservoirs. Additionally, the heat spreader and die may be coupled during a reflow process where the gaseous pressure surrounding the integrated heat spreader and the die is varied.