Abstract: A method of fabricating a semiconductor device having high output power and excellent long-term reliability by preventing thermal adverse influence exerted at the time of window structure formation is provided. The method comprises a 1st step of forming predetermined semiconductor layers 2 to 9 containing at least an active layer 4b consisting of a quantum well active layer on a semiconductor substrate 1; a 2nd step of forming a first dielectric film 10 on a first portion of the surface of the semiconductor layers 2 to 9; a 3rd step of forming a second dielectric film 12 made of the same material as that of the first dielectric film 10 and having a density lower than that of the first dielectric film 10 on a second portion of the surface of the semiconductor layers 2 to 9; and a 4th step of heat-treating a multilayer body containing the semiconductor layers 2 to 9, the first dielectric film 10, and the second dielectric film 12 to disorder the quantum well layer below the second dielectric film 12.

Abstract: An integrated circuit device includes a substrate including a trench therein and a conductive plug wire pattern in the trench. The conductive plug wire pattern includes a recessed portion that exposes portions of opposing sidewalls of the trench, and an integral plug portion that protrudes from a surface of the recessed portion to provide an electrical connection to at least one other conductive wire pattern on a different level of metallization. A surface of the plug portion may protrude to a substantially same level as a surface of the substrate adjacent to and outside the trench, and the surface of the recessed portion may be below the surface of the substrate outside the trench. Related fabrication methods are also discussed.

Abstract: A non-ESL semiconductor interconnection structure and a method of forming the same are provided. The non-ESL semiconductor interconnection structure includes a first low-k dielectric layer comprising a first region and a second region overlying the substrate, a plurality of conductive features in the first low-k dielectric layer, a cap layer on at least a portion of the conductive features, and a dielectric capping layer overlying the first low-k dielectric layer in the second region but not in the first region. The conductive features in the second region have a substantially greater spacing than the conductive features in the first region. The dielectric capping layer preferably has an inherent compressive stress.

Abstract: A memory device in which both DRAM and phase-change memory (PCRAM) are mounted is provided with a DRAM bit line, a PCRAM bit line or a PCRAM source line formed on an conductive layer shared with the DRAM bit line, and a sense amplifier connected between the DRAM bit line and the PCRAM bit line. The memory device further has a capacitive element disposed on the upper layer of the DRAM bit line, and a phase-change element disposed on the upper layer of the PCRAM bit line. The lower electrode of the capacitive element and the lower electrode of the phase-change memory element are formed on the shared conductive layer.

Abstract: The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

Abstract: A method of removing a spacer, a method of manufacturing a metal-oxide-semiconductor transistor device, and a metal-oxide-semiconductor transistor device, in which, before the spacer is removed, a protective layer is deposited on a spacer and on a material layer (such as a salicide layer) formed on the source/drain region and a gate electrode, such that the thickness of the protective layer on the spacer is smaller than the thickness on the material layer, and thereafter, the protective layer is partially removed such that the thickness of the protective layer on the spacer is approximately zero and a portion of the protective layer is remained on the material layer. Accordingly, when the spacer is removed, the material layer may be protected by the protective layer.

Abstract: Disclosed is a semiconductor structure and associated method of performing the structure with good performance and stability trade-offs for digital circuits and SRAM cells and/or analog FETs on the same chip. Specifically, a dual-strain layer is formed over digital circuits and the other devices on a chip. The dual-strain layer comprises tensile sections above digital logic n-type transistors, compressive sections above digital logic p-type transistors and additional tensile sections above SRAM cells and/or analog FETs. An amorphization ion-implant is performed to relax the strain over SRAM cell p-FETs and, thereby, eliminate variability and avoid p-FET performance degradation in the SRAM cells. Additionally, this ion-implant can relax the strain above both analog p-FETs and n-FETs and, thereby, eliminate variability and the coupling of the logic device process to the analog FETs and provide more predictable and well-controlled analog FETs.

Abstract: A pixel electrode is disposed to cover the inner surfaces of a pixel-drain contact hole passing through a third insulating film and a second insulating film to reach a drain electrode. At the bottom of the pixel-drain contact hole, the pixel electrode is electrically connected with the drain electrode through a contact conductor film. The pixel-drain contact hole is formed of a connection of a contact hole passing through the second insulating film and a contact hole passing through the third insulating film. The dimensions of the opening end of the contact hole are larger than its dimensions at the bottom, and thus the inner surfaces of the contact hole are smoothly sloped and shaped like a crater in cross section.

Abstract: The invention is directed to particular polymer compositions that may be generally characterized by the formula: wherein the variables L, M and N represent the relative molar fractions of the monomers and satisfy the expressions 0<L?0.8; 0<M?0.25; 0<N?0.35; and L+M+N=1; and, wherein R1, R2 and R3 are independently selected from C1-C6 alkyls and derivatives thereof. The invention is also directed to polymer compositions that, when used to form a buffer layer or pattern, can be more easily removed from the surface of a semiconductor substrate, thereby increasing productivity and/or reducing the likelihood of defects and failures associated with residual photoresist material.

Abstract: A method for analyzing a sample for the manufacture of integrated circuits, e.g. MOS transistors, application specific integrated circuits, memory devices, microprocessors, system on a chip. The method includes providing an integrated circuit chip, which has a surface area with at least one region of interest, e.g., bond pad. The method includes covering a first portion of the surface area including the region of interest using a blocking material. The method also forms a metal layer on a second portion of the surface area, while the blocking material protects the first portion. The method removes the blocking material to expose the first portion of the surface area including the region of interest. The method also subjects the metal layer to a voltage differential to draw away one or more charged particles from the first portion of the surface area. The method also subjects the surface area including the region of interest to spectrometer analysis.

Abstract: It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.

Abstract: A rearview mirror system), in particular for a motor vehicle, including a rearview mirror provided with a reflection part with variable reflectance and a control system associated with the reflection part and including a number of illuminance sensors, configured for a particularly reliable determination of a nominal value for the reflectance which is adapted to the situation and to the requirements. The spectral response of an illuminance sensor provided as a glaring-illuminance sensor is configured to provide a response characteristic shifted towards shorter wavelengths as compared to a scotopic eye response characteristic. Advantageously, the spectral response of a further illuminance sensor provided as a glaring-illuminance sensor, in the manner of a double sensor design, may be configured to provide a response characteristic shifted towards longer wavelengths as compared to the scotopic eye response characteristic.

Abstract: Provided are a stack semiconductor package manufactured by multiple molding that can prevent the breakage due to stress concentration at a connecting portion between separate semiconductor packages and a method of manufacturing the same. The stacked semiconductor packages are combined together through sealing resins by molding them multiple times, resulting in uniform stress distribution across substantially the entire interface between the semiconductor packages.

Abstract: A semiconductor device includes: a semiconductor substrate having first and second semiconductor layers; an IGBT having a collector region, a base region in the first semiconductor layer, an emitter region in the base region, and a channel region in the base region between the emitter region and the first semiconductor layer; a diode having an anode region in the first semiconductor layer and a cathode electrode on the first semiconductor layer; and a resistive region. The collector region and the second semiconductor layer are disposed on the first semiconductor layer. The resistive region for increasing a resistance of the second semiconductor layer is disposed in a current path between the channel region and the cathode electrode through the first semiconductor layer and the second semiconductor layer with bypassing the collector region.

Abstract: An external light-shielding layer capable of enhancing a visible light transmittance and a contrast ratio and preventing Moiré fringe and Newton ring phenomena, a display filter including the external light-shielding layer, and a display device including the display filter. The external light-shielding layer includes a transparent resin matrix, and a plurality of light-shielding patterns formed on the transparent resin matrix and spaced apart from each other in a predetermined interval, wherein a bias angle (?) formed between a traveling direction of the light-shielding patterns and the longer side of the matrix is in a range of about 5 to 80 degrees.

Abstract: Capacitors are disclosed having reduced parasitic capacitance. In one embodiment, the capacitor includes a first set of electrodes, each electrode of the first set extending through at least one of a plurality of back-end-of-line (BEOL) layers above a substrate; a second set of electrodes, each electrode of the second set extending through at least one of the BEOL layers, and wherein each electrode of the second set extends to a greater depth of the plurality of BEOL layers than each electrode of the first set.

Abstract: A low voltage power device includes a plurality of quasi-vertical LDMOS device cells. A conductive trench sinker is formed through the epitaxial layer and adjacent a selected one of the source and drain regions in each cell. The trench sinker electrically couples the selected one of the source and drain regions to the substrate for coupling current from the channel to the substrate. The resulting device exhibits a vertical current flow between the metal electrode covering the front surface and the second electrode formed at the back side of the wafer. The device cells are arranged in a closed cell configuration.

Abstract: A method is provided for fabricating a semiconductor component that includes a capacitor having a high capacitance per unit area. The component is formed in and on a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The method comprises forming a first capacitor electrode in the first semiconductor layer and depositing a dielectric layer comprising Ba1-xCaxTi1-yZryO3 overlying the first capacitor electrode. A conductive material is deposited and patterned to form a second capacitor electrode overlying the dielectric layer, thus forming a capacitor having a high dielectric constant dielectric. An MOS transistor in then formed in a portion of the second semiconductor layer, the MOS transistor, and especially the gate dielectric of the MOS transistor, formed independently of forming the capacitor and electrically isolated from the capacitor.

Abstract: An electric-magnetic field-generating element and a multipole element comprising a plurality of these field-generating elements providing for a stable charged particle beam are described. For some embodiments, the electric-magnetic field-generating element includes a pole piece, a yoke to which the pole piece is attached, at least one coil, a vacuum-tight container accommodating the coil(s), and a holder adapted to hold the vacuum-tight container such that the vacuum-tight container is spaced from the pole piece and the yoke.

Abstract: A floor track fitting for securing seating or other equipment to a section of aircraft floor track consists of a pair of substantially U-shaped cleat members and a captive bolt. The cleat members are inserted back-to-back through the holes in the floor track. Once the cleat members are in place, a cover is placed over the cleat members so that the captive bolt passes through the top of the cover. The inside of the cover has a pair of integral spaces that force the cleat members outward against the sides of the track channel holes so that the undercut portion of the cleat members locks onto the underside of the floor track. As the bolt is tightened it presses down on the cover and simultaneously draws the cleat members upward against the underside of the floor track to clamp the floor track firmly between the cleat members and the cover.