Abstract: The decision to prefetch inodes is based upon the detecting of access patterns that would benefit from such a prefetch. Once the decision to prefetch is made, a plurality of inodes are prefetched in parallel. Further, the prefetching of inodes is paced, such that the prefetching substantially matches the speed at which an application requests inodes.

Abstract: A method, device, and system are disclosed. In one embodiment, the method comprises setting a threshold length for data allowed in a cache, inserting data into the cache during a read or a write request if the length of the data requested is less than the threshold length, and not inserting data into the cache during a read or write request if the length of the data requested is greater than or equal to the threshold length.

Abstract: A method and an apparatus to reduce network utilization for source-based snoopy cache coherent protocols have been disclosed. In one embodiment, the method includes receiving at a first processor an invalidating snoop with respect to a physical address of a portion of a memory in a multiprocessor system from a second processor, checking whether a cache of the first processor stores a copy of data associated with the physical address, and recording an identification (ID) of the second processor if the cache of the first processor stores the copy of data associated with the physical address. Other embodiments have been claimed and described.

Abstract: Briefly, in accordance with one embodiment of the invention, a portable communication device may have multiple processors and a memory. Portions of the memory may only be accessible by one of the processors.

Abstract: A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical location in the data array block during a CAM search-and-compare operation a register for storing a user defined priority value assigned to each PE block and means for evaluating priority values and the address determined by the plurality of PE blocks to select a PE block having the highest priority data entry.

Abstract: Resources of a storage apparatus are utilized effectively by increasing and reducing a capacity of a differential LU used in a snapshot. In a disk array apparatus including a control processor which controls reading and writing of data with respect to a first logical volume which is generated using storage areas of a plural disk drives, performs control such that data in the past stored in the first logical volume is written in a second logical volume as differential data for each generation, and manages the differential data, the control processor manages a pool management table, in which a logical volume usable as the second logical volume is registered, and a pool addition object management table, in which a logical volume which can be added to the second logical volume is registered, and moves the logical volume from the pool addition object management table to the pool management table to thereby increase a capacity of the second logical volume.

Abstract: An electronic system comprises a control unit for ordering the storage of an index value for indexed registers, in an additional index register linked to a defined initiator module, in response to a request to write the index value in an index register linked to the indexed registers, initiated by the initiator module. In response to any request to access an indexed register initiated by a defined initiator module, the control unit copies the index value from the additional index register linked to this initiator module to the index register linked to this indexed register, prior to execution of the access request. This enables management of access to indexed registers associated with an arbitration mechanism provided for managing conflicting access requests initiated by different functional modules in a system on a chip.

Abstract: A cache memory system may be is organized as a set of numbered banks. If two clients need to access the cache, a contention situation may be resolved by a contention resolution process. The contention resolution process may be based on relative priorities of the clients.

Abstract: A method, apparatus, and computer instructions for transferring data. The data in a first partition is received within a memory region assigned to the first partition in the logical partitioned data processing system to form received data. The memory region is assigned to a second partition, in response to a determination that the received data is for the second partition. The second partition may then access the data in the memory region.

Abstract: A method for managing an external memory of a microprocessor so that the external memory only contains one copy of a common area. By providing an address translator, mapping the page and the address of the common area of the page pointed by a microprocessor to the physical address of the common area of the external memory, using the address translator to translate a page and an address pointed by a microprocessor to a physical address of the external memory, and using the microprocessor to access data stored at the physical address of the external memory; the memory can be more efficiently used.

Abstract: An electronic system comprises an initiator module and a target module addressable by the initiator module, and an interface and control module for interfacing between respective communication protocols of the initiator module and of the target module. The interface and control module is constructed to set a composite instruction detection signal in response to the detection of a composite instruction executed by the initiator module, which composite instruction detection signal is used for the interfacing. The interface and control module is constructed to detect a composite instruction executed by the initiator module when, at a determined clock cycle of the initiator module, a change of the elementary operation executed by the initiator module is detected with respect to the previous clock cycle of the initiator module, while, at the same time, a signal for selecting the target module which was active is kept active.

Abstract: A method for informing a processor of a selected order of transmission of data to the processor. The method comprises the steps of coupling system components via a data bus to the processor to effectuate data transfer, determining at the system component logic the order in which to transmit data to the processor, and issuing to the data bus a selected order bit concurrent with the data, wherein the selected order bit alerts the processor of the order and the data is transmitted in that order. In a preferred embodiment, the system component is the cache and the method may involve receiving at the cache a preference of ordering for a read address/request from the processor. The preference order logic of the cache controller or a preference order logic component evaluates the preference of ordering desired by comparing the processor preference with other preferences, including cache order preference.

Abstract: The present invention is a method for coercing disk drive capacity in a RAID configuration. The method includes the step of determining actual disk drive capacities of a first disk drive and a second disk drive in the RAID configuration. If the actual disk drive capacities of the first disk drive and the second disk drive differ, the method further includes multiplying the smaller actual disk drive capacity by a coercion ratio to establish an optimal disk drive capacity. The optimal disk drive capacity sets a minimum capacity threshold for any disk drive utilized within the RAID configuration. If the actual disk drive capacities of the first disk drive and the second disk drive are an equal value, the method further includes multiplying the value by the coercion ratio to establish the optimal disk drive capacity.

Abstract: A CAM device (100) according to an embodiment can include a control circuit (106) that can sequentially activate, with dummy operations, an increasingly larger number of CAM blocks (102-1 to 102-16) in response to a start-up circuit (104) indication until an initial number of CAM blocks is activated. A control circuit (106) can receive a user configurable block number (USER_BLK) and adjust the number of CAM blocks in a sequentially fashion, with dummy operations, until the user configurable number of CAM blocks is being activated. If a received command is targeted to less than the user configurable block number of CAM blocks, a control circuit (106) can activate, with dummy operations, an additional number of CAM blocks so that the total number of CAM blocks activate equals the user configurable block number.

Abstract: A system and method for writing the same data field to multiple RAM copies during a single write cycle that fans out write data, address data, and control data to multiple RAMs. The multiple copies of data held at the same address in the multiple RAM copies are also read during a single write cycle and the data from each RAM copy is concatenated into a single word that is read during a single read cycle.

Abstract: The present invention proposes a novel cache residence prediction mechanism that predicts whether requested data of a cache miss can be found in another cache. The memory controller can use the prediction result to determine if it should immediately initiate a memory access, or initiate no memory access until a cache snoop response shows that the requested data cannot be supplied by a cache. The cache residence prediction mechanism can be implemented at the cache side, the memory side, or both. A cache-side prediction mechanism can predict that data requested by a cache miss can be found in another cache if the cache miss address matches an address tag of a cache line in the requesting cache and the cache line is in an invalid state. A memory-side prediction mechanism can make effective prediction based on observed memory and cache operations that are recorded in a prediction table.

Abstract: An apparatus and a method for rapidly flushing a cache memory device, including a list structure to track changes in a cache, which may be implemented on the processor die separate from the cache memory. The list structure allows for access to a relatively small store of data to determine whether or not a cache entry needs to be written to the main memory. Choosing the format of the list structure, allows one to make tradeoffs between area needed on a chip and the amount of efficiency in the cache flushing process.

Abstract: Distinguishing between snoops initiated internally with respect to a processing unit and snoops initiated externally with respect to a processing unit allows maintenance of cache coherency for a processing unit with multiple independent cache nits. A processing unit with multiple independent cache units, issues an externally initiated snoop to its cache units. Responses from the multiple independent cache units are the basis for a unified response provided to at least the initiator of the external snoop. An internally initiated snoop is communicated to the host system, and communicated to peer cache unit(s) within the processing unit.

Abstract: An ECU includes a microcomputer that has an integrated flash memory. An initial writing flag is set in the microcomputer before an initial writing to the flash memory. The microcomputer enters into a writing mode when the flag determines permission of data writing. When the data-writing to the flash memory is completed, the flag is cleared.

Abstract: In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each the sector including a user data portion and an overhead portion. The sectors being organized into blocks with each sector identified by a host provided logical block address (LBA). Each block is identified by a modified LBA derived from the host-provided LBA and said virtual PBA, said host-provided LBA being received by the storage device from the host for identifying a sector of information to be accessed, the actual PBA developed by said storage device for identifying a free location within said memory bank wherein said accessed sector is to be stored.