Abstract: A present invention provides a system and method for avoiding memory hazards in a multi-threaded CPU which shares an L-1 data cache. The system includes a CPU and an AACAM. The AACAM is capable of copying memory addresses from the two or more threads being processed by the CPU. The method provides for comparing the AACAM memory address with the active threads to avoid memory hazards by thread switching before the memory hazard occurs.

Abstract: One of the primary difficulties that result from using static variables in multi-threaded computer programs is that changes to a static variable made by one thread will be seen by all other threads operating within the same process. Multiple threads cannot use static variables separately because other threads within the process can overwrite the values stored at the variable memory location. Thus, the development of multi-threaded programs using static variables often requires explicit thread harmonization by the programmer. Another problem is that threads within the same process must use unique static variable IDs to avoid reading or writing to the location of another static variable. This also requires thread harmonization by the programmer. Accordingly, in view of the shortcomings associated with existing thread-static data implementations, there remains a need for an efficient thread-static data implementation that can be used on most modern operating systems.

Abstract: A cache memory for use in a multithreaded processor includes a number of set-associative thread caches, with one or more of the thread caches each implementing an eviction process based on access request address that reduces the amount of replacement policy storage required in the cache memory. At least a given one of the thread caches in an illustrative embodiment includes a memory array having multiple sets of memory locations, and a directory for storing tags each corresponding to at least a portion of a particular address of one of the memory locations. The directory has multiple entries each storing multiple ones of the tags, such that if there are n sets of memory locations in the memory array, there are n tags associated with each directory entry. The directory is utilized in implementing a set-associative address mapping between access requests and memory locations of the memory array.

Abstract: A memory apparatus, such as a memory card, comprising a first storage region and a second storage region. Data can be read from, and written into, the first storage region, in accordance with instructions made by a user. Data can be read from, and written into, the second storage region when a data-processing apparatus, to which the memory apparatus is connected, performs prescribed procedures. Data that should not be easily rewritten or read by users, such as a password or a use history, is stored into the second storage region. The security of the memory apparatus, such as a memory card, can therefore be enhanced.

Abstract: The rewriting device for rewriting data stored in a memory of a vehicle controller with new data is provided. The rewriting device is capable of communicating with the vehicle controller. When deleting or writing operation on the memory is not being performed, the rewriting device determines that communication between the rewriting device and the vehicle controller is offline if no response from the vehicle controller within a first determination time. When deleting operation or writing operation on the memory is being performed, the determination of offline is prohibited until a second determination time has elapsed. The second determination time is greater than the first determination time. It is preferable that the second determination time for deleting operation is the time necessary to delete the data stored in the memory, and that the second determination time for writing operation is the time necessary to write the new data into the memory.

Abstract: A circuit includes a switch unit, an non-protected register and a set of protected control registers. The set of protected control registers stores safe data for use by another unit of the circuit. The switch unit outputs the data stored by one of the set of protected control registers as a function of the data stored by the non-protected register. The data in the non-protected register can be changed by software in response to user input, operational mode or other condition or conditions.

Abstract: Method of operating a computer system with a central processing unit and a hard disk system coupled with the central processor, the method comprising the steps of: partitioning the hard disk into at least a bootable partition and a second partition; determining a write protection for the bootable partition; using the second partition as a write cache thereby maintaining the bootable partition; if a write protection is not set, then flushing the write cache to the bootable partition during a shutdown procedure.

Abstract: The object of this invention is to perform the sorting, compiling and joining of data at extremely high speeds. This is achieved by a distributed memory type information processing system comprising: a CPU module, a plurality of memory modules, each of which having a processor and RAM core, and a plurality of sets of buses that make connections between the CPU and memory modules and/or connections among memory modules, where the processors of the various memory modules execute the processing of arrays managed by the one or more memory modules based on instructions given by the CPU to the processors of the various memory modules.

Abstract: A memory map evaluation tool is provided that organizes a program in a manner most compatible with use of a cache. The tool includes a method that involves executing a first version of the program according to a first memory map to generate a program counter trace, converting the program counter trace into a specific format and then translating the program counter trace into physical addresses using a memory map to be evaluated, different from the first memory map. Those physical addresses are then used to evaluate the number of likely cache misses using a model of a direct-mapped cache for the memory map under evaluation.

Abstract: Disclosed are a method and device (100) for prefetching referenced resources (105) from servers (102, 103, 104). A first resource (106) is scanned for unfetched references (107), which are weighted and prefetched in the order of their weight. The computation of the weight is based on the number of times the resource referenced by the reference has been fetched previously, and on the number of times one or more further resources have been fetched previously from a server that serves the resource referenced by the reference. The device (100) can be realized as a computer program product.

Abstract: A mechanism for managing pointers or handles to transient objects is disclosed. An anonymous token is assigned to an object. When an anonymous token is needed for an object, an unused token value is obtained from a list of available values and is associated with the object, the token value is removed from the list of available values, and data elements of a token data array entry associated with the anonymous token value are updated. When an operation is performed on an object identified by an anonymous token, data elements are evaluated and if reuse counts are not identical or if the validity indicator does not indicate that the object is valid, the operation is not performed. When an object is de-allocated, the token value associated with the object is returned to the available list and the data elements associated with the token value are updated.

Abstract: A method for informing a processor of a selected order of transmission of data to the processor. The method comprises the steps of coupling system components via a data bus to the processor to effectuate data transfer, determining at the system component logic the order in which to transmit data to the processor, and issuing to the data bus a selected order bit concurrent with the data, wherein the selected order bit alerts the processor of the order and the data is transmitted in that order. In a preferred embodiment, the system component is the cache and the method may involve receiving at the cache a preference of ordering for a read address/request from the processor. The preference order logic of the cache controller or a preference order logic component evaluates the preference of ordering desired by comparing the processor preference with other preferences, including cache order preference.

Abstract: A mechanism for maintaining the first-in first-out order of commands in a multiple-input and multiple-output buffer structure includes a command number generator for generating and assigning a command number to each command entering the buffer structure, and a command number comparator for comparing the command number of the outgoing command at each buffer in the buffer structure to determine which command should exit. Both command number generator and command comparator have a cyclic counter that has a period greater than or equal to the total number of allowable buffer entries in the buffer structure. For maintaining order of posted and non-posted command queues, a pending posted write counter is used in the posted command queue to record the number of pending posted write command and each entry in the non-posted command queue is associated with a dependency counter.

Abstract: A data storage device is described that includes a plurality of host interface units, a plurality of disk interface units, and a plurality of disk drive units each coupled to one of the disk interface units. The host interface units may be coupled to one or more external host systems for performing a data operation to a disk drive system. A disk drive unit includes a controller with an onboard memory subdivided into two sections in which one of the sections may be used in connection with performing caching operations of data. The data cached may be from the disk platter associated with the disk drive unit, or, the data cached in the section may also be from another disk drive unit different from the one associated with the disk drive unit in which the section is included. Commands are generated for performing data caching operations to the section of the onboard memory.

Abstract: A proxy partition cache (PPC) architecture and a technique for address-partitioning a proxy cache consisting of a grouping of discrete, cooperating caches (servers) is provided. Client requests for objects (files) of a given size are redirected or reassigned to a single cache in the grouping, notwithstanding the cache to which the request is made by the load-balancing mechanism (such as a Layer 4 switch) based upon load-balancing considerations. The file is then returned to the switch via the switch-designated cache for vending to the requesting client. The redirection/reassignment occurs according to a function within the cache to which the request is directed so that the switch remains freed from additional tasks that can compromise speed.

Abstract: A computer system including a processor, an object cache operatively connected to the processor, a memory, and a translator interposed between the object cache and the memory, wherein the translator maps an object address to a physical address within the memory.

Abstract: A cache management system includes a main memory for storing instructions and information for identifying cache control instructions, a central processing unit (CPU) for executing the instructions, an instruction identifier for identifying that an instruction stored the main memory is a cache control instruction, a cache controller for predicting a next instruction to be executed by the CPU and for reading a corresponding program information in advance when the cache control instruction is identified by the instruction identifier, and a cache memory for storing executable instructions and data from the main memory and for supplying the executable instructions to the CPU under the control of the cache controller.

Abstract: A method and circuit for fast memory access (read or write) of the data to and from a memory array is disclosed. Architecture wise, the memory array control circuit provides for at least two address latches and two page registers. The first address latch contains a first data address and the second address latch contains a second data address. The first data address is decoded first and sent to the memory array to access (read or write) the corresponding data from the memory array. When the data of the first data address is being accessed, the decoding process will begin for a second data address. When the data of the first data address has been accessed, the second data address is ready for the memory array. Thus, there can be continuous fetching from or writing to the memory array. In the preferred embodiment, there are two page registers. In a read operation, the data read from the first data address is transferred to a first page register.

Abstract: A method for operating a cache having a sleep mode is provided. The cache is located within a memory hierarchy of a computer system, and the method is comprised of receiving a first cache request, and servicing the first cache request. A sleep mode signal is asserted in response to completion of the servicing of the first cache request. Thereafter, a second cache request is received, and the sleep mode signal is deasserted in response to receiving the second cache request. Thereafter, the second cache request is serviced.

Abstract: A unified tag subsystem for a multilevel cache memory system. The unified tag subsystem receives a cache line address including a tag index portion, a high order part and an optional cache line extension field. The tag index portion indexes a tag memory which has way-specific address tags, and lower level flags. A comparator compares the high order part with each way-specific address tag to detect a match. Lower level hit logic determines a hit when comparator detects a match and the lower level flag indicates a valid lower level cache entry; and an upper level hit logic determines a higher level cache hit when the comparator detects a match and the upper level valid is set. In particular embodiments, lower level flag indicates a way of storage where associated data may be found in lower level cache data memory.