Patents Examined by Kourosh Cyrus Khosravi
  • Patent number: 5650732
    Abstract: A semiconductor device test system for efficiently testing many types of devices and for reducing the amount of floor space needed. The test system has a test board having a plurality of sockets for receiving semiconductor devices. A semiconductor device insertion and extraction station removes the devices from a tray and inserts them into the sockets of the test board and extracts the devices from the sockets to mount them on the tray. A test chamber has a temperature setting section for setting the test board to a test environmental temperature and a test-performing section for supporting the test board so that electrode terminals of the sockets are exposed. A tester head is simultaneously connected to the electrode terminals of the sockets of the test board. A head moving section connects the tester head to the electrode terminals of the sockets of the test board. A tester is connected to the tester head to test electrical characteristics of the semiconductor devices.
    Type: Grant
    Filed: June 28, 1994
    Date of Patent: July 22, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Iwao Sakai
  • Patent number: 5625300
    Abstract: An IC is tested through I.sub.DDQ -measurements. The IC's substrate includes a region of a conductivity type with a supply node for supply of the circuit and with a biasing node for connection to a biasing voltage to bias the region. I.sub.DDQ -testing of the circuit is conducted while the supply node and the biasing node are galvanically disconnected to separate the contribution to the quiescent current from the circuit functionality features from the contribution to the quiescent current from the biasing features.
    Type: Grant
    Filed: December 14, 1994
    Date of Patent: April 29, 1997
    Inventor: Manoj Sachdev
  • Patent number: 5585736
    Abstract: A contact probe for semiconductor in-line process monitoring or device measurement is disclosed in this invention which uses gallium, indium or any low-melting and low-vapor pressure electrically conductive alloy as a contact probing material. The probe can be used to directly measure mobile ion density without requiring the formation of aluminum dots on the semiconductor wafers. The safety issues caused by high temperature operation are also eliminated. The time requirement for process-equipment qualification is significantly reduced because the preparation time for aluminum dot formation is now eliminated. In comparison to the mercury probes, since in this invention, the contact is formed at high temperature thus leading to better contacts between the probe and the wafer, which in turn resulting in higher measurement accuracy. Furthermore, the conventional pin slip problem during elevated temperature stress is eliminated by the use of the contact probe of this invention.
    Type: Grant
    Filed: November 29, 1994
    Date of Patent: December 17, 1996
    Assignee: Fwu-Iuan Hshieh
    Inventors: Fwu-Iuan Hshieh, Calvin Choi, Yoeh-Se Ho, Jimmy S. X. Weang
  • Patent number: 5568054
    Abstract: A probe apparatus having a burn-in test function includes an apparatus body, a probe card, having a plurality of probes, for causing the plurality of probes to electrically contact a semiconductor wafer, a tester for measuring the electrical characteristics of the semiconductor wafer, heating and cooling mechanisms for applying a thermal stress to test target chips, as targets of the burn-in test, of the semiconductor wafer, and an electrical mechanism for applying an electrical stress to the chips.
    Type: Grant
    Filed: May 19, 1995
    Date of Patent: October 22, 1996
    Assignees: Tokyo Electron Limited, Tokyo Electron Yamanashi Limited
    Inventors: Shinji Iino, Itaru Iida
  • Patent number: 5565788
    Abstract: A shielded microwave probe tip assembly includes an end of a coaxial cable coupled to probe fingers forming a coplanar controlled impedance microwave transmission line where the ground probe fingers are interconnected by a shield member that is spaced apart from the signal line probe finger but is positioned between the signal line probe finger and a device under test. The shield prevents the generation of extraneous signals or parasitic coupling from the device under test which would otherwise degrade measurement accuracy.
    Type: Grant
    Filed: May 12, 1995
    Date of Patent: October 15, 1996
    Assignee: Cascade Microtech, Inc.
    Inventors: Jeremy Burr, Gregory Nordgren, Eric W. Strid, Kimberly R. Gleason
  • Patent number: 5563509
    Abstract: An adapter unit configurable for testing ICs having different power and ground contact configurations is customized for one of such configuration and mounted on a load board having first and second plurality of signal contacts, wherein respective pairs of the first and second plurality of signal contacts are connected to both a contact of the IC and a test channel from an IC tester. The adapter unit is mounted on the load board making contact with the first plurality of signal contacts, while a DUT board holding the IC is mounted on the load board making contact with the second plurality of signal contacts. The adapter unit includes a plurality of signal contacts respectively connected to the first plurality of signal contacts of the load board, a power bus ring connected to a power line provided by the IC tester, and a ground bus ring connected to a ground line from the IC tester.
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: October 8, 1996
    Assignee: VLSI Technology, Inc.
    Inventor: Gary L. Small
  • Patent number: 5559446
    Abstract: A probing device for inspecting semiconductor devices such as IC chips includes a mounting section for supporting a silicon substrate wafer (i.e., an object to be inspected), a moving section for moving a probe card in such a way that contacts formed on a surface of the probe card can be pushed against electrode pads formed on the wafer, and a measuring section. The probe card is formed by joining a silicon nitride (Si.sub.3 N.sub.4) thin film (whose thermal expansion coefficient is roughly equal to that of the silicon wafer) to a lower surface of a wiring substrate. The wiring substrate is composed of a polyamide thin film (as an insulating layer) and conductive layers (as conductive signal line paths) formed in and on both the surfaces of the polyamide thin film. Further, bumps (contacts) are arranged on the lower surface of the silicon nitride thin film.
    Type: Grant
    Filed: July 18, 1994
    Date of Patent: September 24, 1996
    Assignees: Tokyo Electron Kabushiki Kaisha, Tokyo Electron Yamanashi Kabushiki Kaisha
    Inventor: Kunio Sano
  • Patent number: 5555422
    Abstract: One type of a prober for use in making measurement or aging of electric circuit elements and parts such as semiconductor integrated circuits is used for testing the electrical performance of semiconductor integrated circuit elements formed on the semiconductor substrate, and comprises a prober substrate of which thermal expansion coefficient is substantially same as that of the semiconductor substrate. The prober substrate has a plurality of leads at its center portion, said leads correspond to the pads of the semiconductor integrated circuit element, each lead has a contact to abut on the corresponding pad, and said prober substrate has conductive layers formed thereon each having one end extending to said contact and other end terminating in the vicinity of the circumference of the prober substrate.
    Type: Grant
    Filed: October 24, 1995
    Date of Patent: September 10, 1996
    Assignee: Co-operative Facility for Aging Tester Development
    Inventor: Shoukichi Nakano
  • Patent number: 5554939
    Abstract: The present invention provides a novel sensor preferably used for non-destructive measurement of the electrical characteristics of semiconductors. The sensor is easily manufactured and has a sufficiently high dielectric breakdown strength. The sensor includes an electrode mount 64 having a an electrode pattern 200 formed on a bottom surface 66a of a cone glass 66. The bottom surface 66a has a reflecting plane 66c for reflecting a laser beam, a test electrode 201, and three parallelism adjustor electrodes 111 through 113 formed around the reflecting plane 66c. The bottom surface 66a also has a guard ring 120 disposed between the test electrode 201 and the parallelism adjustor electrodes 111 through 113. An insulating film 68 covers a lower surface of the cone glass 66. Wiring formed on a inclined face 66b of the cone glass 66 is connected to external lead wires at the upper end of the wiring.
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: September 10, 1996
    Assignee: Dainippon Screen Manufacturing Co., Ltd.
    Inventors: Sadao Hirae, Hideaki Matsubara, Motohiro Kouno, Takamasa Sakai
  • Patent number: 5552718
    Abstract: This describes a test pattern and method for measuring dimensional characteristics of features formed on a surface. This is realized and provided by forming a space, defined by the feature, in intersecting relationship with a pair of conductive lines of a test pattern configuration such that the lines are altered at the intersection with the space in accordance with the dimensions of that space, measuring the resistance of at least one of the lines in a region remote from the intersection with the space and the resistance of each line in the region of its intersection with the space, and comparing the resistance of the remote region with the resistances for the region of each of the lines where they intersect the space to thereby establish the position of, and at least one dimension of that space.
    Type: Grant
    Filed: January 4, 1995
    Date of Patent: September 3, 1996
    Assignee: International Business Machines Corp.
    Inventors: James A. Bruce, Michael S. Hibbs, Robert K. Leidy
  • Patent number: 5550466
    Abstract: An electronic circuit tester for measuring the response of electrical signals applied to an electronic circuit under test is provided with a pivotable connection for conduit through which cables are routed from a test head coupled to the electronic circuit under test to the remainder of the tester. The test head includes a chassis having a relieved region in which a bracket is selectively mounted. The bracket has first and second legs disposed at a distance from one another, the first and second legs each being provided with an approximately circular hole to provide a bearing surface for pivotable movement. A fitting having first and second approximately tubular arms extending outwardly from an integral transversely depending conduit portion is connected to the chassis with each of the first and second arms rotatably captured in the holes of the respective first and second legs of the bracket when the bracket is mounted to the chassis.
    Type: Grant
    Filed: September 30, 1994
    Date of Patent: August 27, 1996
    Assignee: Hewlett-Packard Company
    Inventor: Julius K. Botka
  • Patent number: 5550479
    Abstract: In a signal measuring apparatus a distance between a sample and a probe is adjusted, a voltage is applied through the sample and the probe and a signal is measured using a current flowing through the sample and the probe. That is, a current flowing through the sample and the probe is chopped by a laser beam at a prescribed frequency and is fetched into a sampling apparatus to generate a sample value of the current. The sample value is compared with a current setting value arbitrarily set in a comparator, and a reference voltage is generated according to a compared result in a control logic circuit and a D/A converter. The reference voltage is fed back to the sampling apparatus to converge the current flowing through the sample and the probe at the current setting value. Therefore, a signal of the sample is measured according to the reference voltage on condition that the current is converged at the current setting value.
    Type: Grant
    Filed: July 6, 1995
    Date of Patent: August 27, 1996
    Assignees: Fujitsu Limited, Advantest Corporation
    Inventors: Shinichi Wakana, Kazuyuki Ozaki, Yoshiro Goto, Yasutoshi Umehara
  • Patent number: 5545975
    Abstract: A storm monitoring apparatus and method is described wherein two H-field antennas are oriented with respect to the heading axis of an aircraft or the like at an angle of 45.degree.. The signals developed by these two antennas are picked-up by small R-F transformers which serve the inherent function of integrating the signals and extracting the H-field current component. A printed circuit board structuring of the two antennas provides for consistency of fabrication and reliability as well as compactness. The monitoring apparatus exhibits broad band frequency response to evaluate lightning strike rate to determine storm range and intensity. A computer control test utilizing diagnostic coils at the antenna carries out periodic testing of the performance of the device and a component such as a gravity switch provides an indication to the control system as to the orientation of mounting of the antenna on an aircraft.
    Type: Grant
    Filed: May 11, 1995
    Date of Patent: August 13, 1996
    Inventor: John S. Youngquist
  • Patent number: 5541502
    Abstract: A level measuring set for low-frequency signals with superimposed direct voltage includes a low-pass filter, a measuring rectifier, and a subtractor. A low-frequency measurement signal is supplied to the low-pass filter, which outputs a reference potential (U.sub.B) which corresponds to the direct voltage. The reference potential (U.sub.B) is applied to a reference point of the measuring rectifier. The measuring rectifier forms a positive and a negative direct voltage component (+U.sub.M, -U.sub.M) superimposed on the reference potential (U.sub.B) for the positive and negative half-waves of the low-frequency signal, respectively. The subtractor receives at inputs thereof the positive and negative direct voltage components (+U.sub.M, -U.sub.M) superimposed by the reference potential (U.sub.B) and emits a level measurement value of the low-frequency measurement signal.
    Type: Grant
    Filed: February 13, 1995
    Date of Patent: July 30, 1996
    Assignee: Siemens Aktiengesellschaft
    Inventor: Klaus Hoffmann
  • Patent number: 5537052
    Abstract: A system and method for executing on board diagnostics in connection with automated test hardware and maintaining an event history on a circuit board having a microprocessor and diagnostic routines stored in read only memory (ROM). The testing of a circuit board by automated test equipment causes a microprocessor on the circuit board to execute the diagnostic routines stored in read only memory on the circuit board. Upon completion of the diagnostic routines, the results generated by the routines are stored in non-volatile memory (NVRAM) on the circuit board. Upon completion of the remaining circuit board testing, the results of that testing are also written to the non-volatile memory on the circuit board. Other events occurring during in the production and use of the circuit board may also be written to the non-volatile memory on the circuit board to maintain a log for diagnostic and statistical purposes.
    Type: Grant
    Filed: June 17, 1994
    Date of Patent: July 16, 1996
    Assignee: EMC Corporation
    Inventors: Robert Wilson, Harold F. Pritoni, Jr.
  • Patent number: 5537030
    Abstract: A portable test set for testing the voltage regulators used by utilities in the power distribution industry for regulating a voltage level of electrical power supplied over a transmission line comprises a first electrical lead adapted for connection to the source bushing on the regulator, a second electrical lead adapted for connection to the load bushing on the regulator, and a third electrical lead adapted for connection to the S/L bushing on the regulator. The test set also includes an electrical terminal adapted for connecting a voltage continuity tester between the second lead and the third lead, an electrical terminal adapted for connection to an alternating current source, and an electrical terminal adapted for connection to a voltmeter.
    Type: Grant
    Filed: July 21, 1994
    Date of Patent: July 16, 1996
    Assignee: Union Electric Company
    Inventors: Douglas E. Snodgrass, William L. Haffecke
  • Patent number: 5534788
    Abstract: A leadframe for sensing electrical parameters in an integrated circuit package includes an interconnect pattern having a plurality of patterned conductive pads connected to a plurality of leads for connecting to an integrated circuit and a resistor which is integral with the leadframe and connects selected conductive pads to form a resistive connection between two of the leads.
    Type: Grant
    Filed: December 9, 1994
    Date of Patent: July 9, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Gregory J. Smith, David J. Kunst
  • Patent number: 5534784
    Abstract: A method for probing a semiconductor wafer utilizes an array probe assembly (60) which includes a production package substrate (64). Substrate (64) is used to transform a configuration of conductive pads (74) on a probe card (62) into a configuration which matches that of conductive bumps (54) on a semiconductor die (52). Array probe assembly (60) may also include an array probe head (68) having probe wires (84) for coupling conductive pads (80) on substrate (64) with conductive bumps (54) on die (52). After probing the die, the die are assembled into a final packaged semiconductor device (110) which includes a substrate (90) which is nearly identical to the substrate used in the array probe assembly. Use of a production package substrate in the array probe assembly reduces the cost of the array probe assembly, and results in more accurate testing since the substrate in the array probe assembly will emulate the performance of the die in the final packaged device.
    Type: Grant
    Filed: May 2, 1994
    Date of Patent: July 9, 1996
    Assignee: Motorola, Inc.
    Inventors: Thomas F. Lum, James F. Wenzel
  • Patent number: 5532612
    Abstract: Methods and specially adapted reusable test carriers provide for burn-in test of semiconductor integrated circuit devices and economical production of known good dice (KGD). Methods for temporary flip-chip mounting of IC wafers or dice use a hierarchy of solder melting points in combination with improved reusable carrier substrates. IC chip wafers having high-melting-temperature flip-chip terminals are coated with a predetermined volume of a sacrificial solder having a significantly lower melting temperature. A reusable temporary carrier is provided, in a range of sizes adapted for a wafer, small numbers of IC dice, or an individual die, For full-wafer burn-in, the reusable carrier has edge connector terminals. For testing individual dice or a small number of dice, the reusable carrier has conductive elements in a pattern matching each IC dies terminal pattern. The same or opposite side of the reusable carrier has pins or ball-grid array matching a conventional burn-in socket.
    Type: Grant
    Filed: July 19, 1994
    Date of Patent: July 2, 1996
    Inventor: Louis H. Liang
  • Patent number: 5532581
    Abstract: In a connector apparatus employed in a measuring system, a sensor is connected by releasable connector to a measuring unit to form a standard sensor connection eliminating any requirement for calibration. The connector apparatus includes a measuring circuit containing a setting line scanning program reading a plurality of setting switches in the connector set in ON/OFF states indicating the type of sensor and correction data employed by the scanning program for measurements made by the sensor.
    Type: Grant
    Filed: May 10, 1994
    Date of Patent: July 2, 1996
    Assignee: Otax Co., Ltd.
    Inventors: Tadahiro Ohkura, Toshiyuki Yoshida, Mitsuru Kainuma, Kazuo Aoki