Patents Examined by Kourosh Cyrus Khosravi
  • Patent number: 5502374
    Abstract: A power measuring system includes a transformer that produces a voltage signal in response to the presence of a changing current within a power cable. An input circuit is electrically connected to the transformer for receiving the voltage signal, and produces an analog current signal representative of the changing current within the power cable, in response to receiving the voltage signal. A transmission line has a first end electrically interconnected with the input circuit so as to receive the analog current signal and has a second end electrically interconnected with an output circuit located at a location remote from the first end. The output circuit receives the analog current signal and produces a resultant signal in response to receiving the analog current signal. The resultant signal may be used to provide a meter display. A housing for a sensing transformer having a split toroidal core is disclosed.
    Type: Grant
    Filed: September 2, 1994
    Date of Patent: March 26, 1996
    Assignee: Veris Industries, Inc.
    Inventor: Roger S. Cota
  • Patent number: 5502398
    Abstract: In a semiconductor device burn-in apparatus, a film on which a plurality of TAB products, each having a semiconductor device thereon, are arranged in succession and a flexible tape-like wiring board which is situated in the same plane as, and in parallel to, the film and on which electrically conductive wiring patterns are formed are detachably clamped by sockets, in units of one of the TAB products. The film and the wiring board are electrically connected by a wiring board provided on each socket. The film, wiring board and socket are stored in a storage member as a combined structure having an elongated shape, and the combined structure is subjected to a burn-in process.
    Type: Grant
    Filed: September 15, 1994
    Date of Patent: March 26, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinobu Wada
  • Patent number: 5502373
    Abstract: An electric current is measured by a device that includes a magneto-optical element which acts as a Faraday rotator wherein a plane of polarization of polarized light passing therethrough is rotated as a function of a magnetic field surrounding that element. A light emitter and polarizer send a polarized light beam through the magneto-optical element. First and second light detectors are located within the single beam of light emerging from the magneto-optical element. Associated with the two detectors are separate polarizers respectively oriented at -45 degrees and +45 degrees to a polarization plane of the light beam emerging from the magneto-optical element when no electric current flows through the conductor. The magnitude of the current in the conductor is determined by comparing signals from the two light detectors.
    Type: Grant
    Filed: June 15, 1994
    Date of Patent: March 26, 1996
    Assignee: Eaton Corporation
    Inventors: Lawrence J. Ryczek, Ruth E. Hubbell
  • Patent number: 5500587
    Abstract: An E-O probe with improved spatial resolution has a light transmissive base part, an electro-optic material which is fixed to the base part and has an index of refraction which varies in response to an electrical field from a measured object, and a mirror which is fixed to the electro-optic material and reflects an incident beam penetrating the base part and the electro-optic material. The mirror is formed to be smaller than the incident beam in diameter. The electro-optic material is formed very thin.
    Type: Grant
    Filed: September 9, 1993
    Date of Patent: March 19, 1996
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Hironori Takahashi, Shinichiro Aoshima, Isuke Hirano
  • Patent number: 5500606
    Abstract: A test fixture including top and bottom probe plates including double-ended pogo pins interfacing top and bottom interface printed circuit board (IPCBs), further including double-ended transfer pins to achieve a true wireless dual access test fixture. The top transfer pins electrically engage the bottom transfer pins after vacuum is applied to allow electrical interface with the top-side fixture without the use of wires. The top fixture mounts in a frame assembly through a parallel linkage keeping the top fixture parallel with the PCB under test. Guide pins mounted on the bottom probe plate are used to align a top plate holding the PCB and also to pre-align with bushings on the top fixture before vacuum is applied. When vacuum is applied, the top plate and top fixture move in a single longitudinal direction to electrically engage the test pins and test pads, preventing lateral movement which heretofore caused significant damage to the test pins and test pads.
    Type: Grant
    Filed: September 16, 1993
    Date of Patent: March 19, 1996
    Assignee: Compaq Computer Corporation
    Inventor: Frederick J. Holmes
  • Patent number: 5500604
    Abstract: A membrane test probe (10) for use in testing integrated circuit chips (50) has a thin flexible membrane (30) bearing test contacts (40,42) that is stretched across an opening of a rigid-flex substrate (12). The membrane is manufactured with uniform radial tension by a lamination fixture having a steel pressure plate (76) that includes an annular groove (78). A high temperature O-ring (80) is positioned in the groove against the radially inner wall (82) of the groove with the radially outer wall of the groove being displaced from the outer part of the O-ring. The O-ring has a thickness greater than the depth of the groove and when the steel pressure plate is pressed against the membrane to press it against its substrate the O-ring pushes a portion (92) of the membrane into a shallow groove (16) in the substrate and deforms radially outwardly. As the O-ring deforms radially outwardly, it exerts a radially outwardly directed tension on the membrane which is cured in this radially stretched condition.
    Type: Grant
    Filed: July 15, 1994
    Date of Patent: March 19, 1996
    Assignee: Hughes Aircraft Company
    Inventors: David B. Swarbrick, Jack H. Pike
  • Patent number: 5498971
    Abstract: A method and circuit for relatively accurately measuring the die temperature of an IC, such as a microprocessor, by sensing one or more internal circuit elements which have an electrical parameter which varies as a function of temperature, such as an input protection diode. By sensing the one or more circuit elements which have an electrical parameter that is temperature dependent, the method provides a relatively more accurate measurement of the die temperature than measuring the outside temperature of the IC package. In addition, a control circuit is provided for cooling the IC during excessive temperature conditions by slowing down the clock frequency of the IC until the die temperature is within the temperature limit in order to optimize the utility of the IC during excessive temperature conditions.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: March 12, 1996
    Assignee: Zenith Data Systems Corporation
    Inventors: Robert R. Turnbull, David J. DeLisle, Robert A. Kohtz
  • Patent number: 5497077
    Abstract: A power calculating device including a control signal generating unit for generating a control signal. The control signal determines a power calculating period and an imbalance compensation period. The device also includes an input voltage changeover unit for changing over between a first voltage corresponding to a voltage of a system under measurement and a constant voltage under the control of the control signal to generate a second voltage, which is the first voltage during the power calculating period and the constant voltage during the imbalance compensation period. The device further includes a Hall element member for generating a third voltage corresponding to a product of the second voltage and a magnetic density generated by a magnetic field applied to the Hall element member. The device also includes an imbalance detecting unit for generating an offset compensation signal based on the third voltage, and a variable resistor connected to the Hall element member.
    Type: Grant
    Filed: July 21, 1994
    Date of Patent: March 5, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tadashi Nukui
  • Patent number: 5493236
    Abstract: A test analysis apparatus for OBIC analysis and luminous analysis from a rear surface of a semiconductor wafer. According to the present invention, a semiconductor wafer is mounted on a wafer chuck and a probe card which has metallic needles and which is movable along the X, Y, and Z axes supplies a test pulse signal to respective electrode pads on the front surface of the semiconductor wafer. Then, current generated in the semiconductor wafer is detected at the electrode pads. Optical analysis, such as irradiation with a light beam, detection of reflected light, detection of light generated in the semiconductor wafer and the like, is performed from the rear side of the semiconductor wafer, thereby enabling analysis of a failure or a defect of a defective portion while the semiconductor wafer is in actual operating conditions.
    Type: Grant
    Filed: June 23, 1994
    Date of Patent: February 20, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tatsuya Ishii, Kazutoshi Miyamoto
  • Patent number: 5493237
    Abstract: This disclosure relates to testing apparatus (10), preferably an LGA burn-in test socket, for an integrated chip (28). The apparatus (10), arranged for mounting on a planar electronic device (46), such as a printed circuit board, includes a frame member (12) for mounting to the planar electronic device (46), where the frame member (12) includes a central opening (22) extending between first and second surfaces, and dimensionally sized to receive the chip (28). Recesses (35) are provided for receiving an electronic interface member (18) mounting plural flexible electrical connectors (106), such as an elastomeric connector, as known in the art, for engaging the traces or pads of the chip to the planar device during testing. Further, plural recesses (40) extend from at least the first surface, where each recess includes a compression spring (41). Positioned over and for engagement with the frame member is a floatably mounted force applying member (14) having first and second parallel surfaces.
    Type: Grant
    Filed: May 27, 1994
    Date of Patent: February 20, 1996
    Assignee: The Whitaker Corporation
    Inventors: Keith L. Volz, Robert M. Renn, Robert D. Irlbeck, Frederick R. Deak
  • Patent number: 5493231
    Abstract: A method and apparatus for measuring the barrier height distribution in an insulated gate field effect transistor by intermittently illuminating a partially transparent gate electrode under bias while applying varying back gate biases to the back gate electrode and measuring the currents conducted by the gate electrode and by the connected source and drain electrodes. Based upon the inverse Laplace transform of the ratio of the measured currents, the barrier height distribution in the transistor, including the average barrier height and the variance of the distribution of barrier heights, typically a Gaussian distribution, may be determined. A method and apparatus for adjusting the gate bias to compensate for variations in the electric field in the insulator layer due to charge generation in the insulator layer is also provided. In addition, the method and apparatus also provides for measuring the photocurrent collected under the gate electrode.
    Type: Grant
    Filed: October 7, 1994
    Date of Patent: February 20, 1996
    Assignee: University of North Carolina
    Inventors: Edward H. Nicollian, Davorin Babic, John C. Lofgren
  • Patent number: 5486754
    Abstract: An electrical current measuring device, for measuring the current in an electrical conductor (11), includes first and second measurement channels. Each of these channels includes a sensor (12) adapted to be located adjacent the conductor (11) and coupled via optical fibers (14,16) to source circuitry (18) and detector circuitry (20). The sensor (12) incorporates a material (22) which exhibits the Faraday magneto-optic effect and the source circuitry (18) is arranged to deliver an unpolarized light signal which is subsequently polarized by a first polarizer (23) to enable a linearly polarized light signal to be incident to the material (22). The quantum of rotation in the plane of polarization imposed on the signal emerging from the material (22) is monitored via a second polarizer (24) by the detector circuitry (20) as a measure of the electrical current flowing in the conductor (11).
    Type: Grant
    Filed: July 21, 1994
    Date of Patent: January 23, 1996
    Assignee: Instrument Transformers Limited
    Inventors: Andrew J. Cruden, James R. McDonald, Ivan Andonovic, Kenneth Allan, Raymond A. Porrelli
  • Patent number: 5486769
    Abstract: In a method and apparatus for measuring quantitative voltage contrast, an electron beam of the scanning electron microscope is located on a specimen electrode, and a grid voltage of an energy analyzer of the scanning electron microscope is varied. A detector detects secondary electron emission from the specimen electrode. A measured peak voltage of the specimen electrode is determined based on output from the detector. A specimen electrode voltage corrected for type I local field effect error is then obtained using the measured peak voltage and a type I calibration curve. The type I calibration curve represents peak voltage versus specimen electrode voltage. Type II local field effect error in the specimen electrode voltage is then corrected based on a type II calibration curve. The type II calibration curve represents a shift in specimen electrode peak voltage versus adjacent electrode voltage.
    Type: Grant
    Filed: August 15, 1994
    Date of Patent: January 23, 1996
    Assignee: National University of Singapore
    Inventors: Wai K. Chim, Jacob C. H. Phang, Daniel S. H. Chan
  • Patent number: 5486758
    Abstract: A variable reluctance magnetic transducer including a tubular housing having a closed end and an open end. A bracket is attached to the outside of the housing a predetermined distance form the closed end of the housing. A core supporting a ferrous metal pole piece and a permanent magnet is disposed within the housing with an end of the pole piece contacting the inside of the closed end of the housing to accurately position the pole piece end relative to the bracket. The core supports a pair of fork terminals which engage arcuate blade terminals carried by a cap assembly. The blade terminals allow positioning of the cap assembly at a plurality of angles relative to the core and housing.
    Type: Grant
    Filed: January 17, 1995
    Date of Patent: January 23, 1996
    Assignee: Kelsey-Hayes Company
    Inventor: Mark K. Hammerle
  • Patent number: 5486772
    Abstract: The present invention detects defects near the gate/trench-surface interface of trench transistors. Defects near this interface which cause long term reliability problems generally also result in charges being trapped near the interface. In accordance with one embodiment of the present invention, a negative voltage is applied to the gate of the trench transistor with its drain grounded and its source floating. A leakage current flowing between the gate and drain is measured as a function of the voltage applied to the gate. A transistor whose gate-drain leakage current exceeds a predetermined value at a specified gate voltage is deemed to be defective. In another embodiment of the present invention, the gate-drain leakage current is measured as described above and monitored over time. Charge accumulated near the gate-drain interface due to defects in the interface results in the gate-drain leakage current taking a longer period of time to fall off to its steady state value.
    Type: Grant
    Filed: June 30, 1994
    Date of Patent: January 23, 1996
    Assignee: Siliconix Incorporation
    Inventors: Fwu-Iuan Hshieh, Calvin K. Choi, William H. Cook, Lih-Ying Ching, Mike F. Chang
  • Patent number: 5486770
    Abstract: An apparatus for probing high frequency electronic devices in wafer form includes a high frequency wafer probe (16, 56) having a conductor (36, 61), a dielectric layer (37, 71, 72), a grounding layer (38, 81, 82, 91), a signal probe needle (39,86), and a pair of ground needles (43, 72, 76) coupled to a substrate (11, 51). A plurality of high frequency wafer probes (16, 56) can be coupled to the substrate (11, 51) to probe high density high frequency electronic devices and to probe high frequency electronic devices having varying bonding pad layouts. The high frequency wafer probe (16, 56) is less sensitive to varying bonding pad height. The apparatus is suitable for probing high frequency electronic devices in a wafer manufacturing environment.
    Type: Grant
    Filed: June 27, 1994
    Date of Patent: January 23, 1996
    Assignee: Motorola, Inc.
    Inventor: Scott V. Johnson
  • Patent number: 5485097
    Abstract: A method of electrically measuring thin oxide thickness by tunnel voltage in a device under test includes the steps of applying a predetermined value of current density through the device under test, measuring voltage developed across the device under test, and calculating the oxide electrical thickness through a predetermined calibration curve. This method is suitable for incorporation into an automatic tester for fast and high volume data collection. This technique also has higher resolution and accuracy than measurements obtained optically.
    Type: Grant
    Filed: August 8, 1994
    Date of Patent: January 16, 1996
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Larry Y. Wang
  • Patent number: 5485079
    Abstract: A magneto-optical element is of a rare-earth iron garnet crystal expressed at least by formula 1, and a element in whose composition range the value of X is set at 0.8.ltoreq.X.ltoreq.1.3; that of Y at 0.2.ltoreq.Y.ltoreq.0.4; that of Z at 0.1.ltoreq.Z.ltoreq.0.9; and that of W at 0.ltoreq.W.ltoreq.0.3; and R element is made at least one or more kinds of rare-earth elements. An optical magnetic field sensor is composed in such a manner that light diffracted by magnetic domain structure of rare-earth iron garnet crystal can be detected up to a higher-order light by optical fiber on light output side through optical system arrangement. A magnetic field measuring equipment composed of the optical magnetic field sensor has a linearity error of .+-.1.0% or less within a magnetic field range 5.0 Oe to 200 Oe, and allows a measuring accuracy higher than with prior art equipment.(Bi.sub.x Gd.sub.y R.sub.z Y.sub.3-x-y-z)(Fe.sub.5-w Ga.sub.w)O.sub.
    Type: Grant
    Filed: March 18, 1994
    Date of Patent: January 16, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Nobuki Itoh
  • Patent number: 5483156
    Abstract: A magnetic field alternation detecting apparatus includes a magnetic member sensor enclosed in a case and having a core (i.e., a yoke) to which a magnet is attached and around which a coil is wound. The magnetic member sensor obtains as an electromotive voltage a change in magnetic flux linking the coil on the basis of a magnetic field distribution disturbed by an approaching magnetic member present near the case from a pair of output terminals of the coil. An analog-to-digital converter is connected to the output terminals of the coil using at least one control terminal of a transistor such as a bipolar transistor or an enhancement operation field effect transistor. A main current terminal of the transistor is connected to a pair of output terminals.
    Type: Grant
    Filed: June 17, 1993
    Date of Patent: January 9, 1996
    Assignee: Fuji Koki Manufacturing Co., Ltd.
    Inventor: Toshihiko Nishihara
  • Patent number: 5483173
    Abstract: A measuring structure includes a first resistor for converting a current to be measured into a voltage, and an operational amplifier for measuring the current. A second resistor connected in series to, and integrated with, the first resistor, is activated by an input terminal solely at the wafer testing stage, to reduce, in relation to the nominal value, the current corresponding to a predetermined voltage value detected by the operational amplifier, and to enable optimum correlation of the reduced current value obtainable during wafer testing and the corresponding nominal current value.
    Type: Grant
    Filed: September 30, 1993
    Date of Patent: January 9, 1996
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventor: Franco Pellegrini