Abstract: A system and methods are provided for mixing input signal data values with values of a sinusoidal waveform. The sinusoidal waveform is normalized at a value greater than one and sampled to generate a fixed set of values for every period of the sinusoidal waveform. The fixed set of values is then converted to a plurality of bit-shift summation sets. The bit-shift summation sets are applied to the input signal by binary shifting the input signal data values. The binary shifts represent a mixing of the fixed set of values associated with the sinusoidal waveform and the input signal values.

Abstract: A method and circuit for facilitating control of the AC coupling for addressing input offset in an amplifier circuit are provided. In accordance with an exemplary embodiment, a control circuit comprises a pair of resistive networks coupled together through a capacitive coupling, with the pair of resistive networks configured between two amplifier devices of the amplifier circuit. The capacitive coupling is configured to prevent offset in the differences between input voltages to the two amplifier devices, and can comprise various types and configurations of capacitor networks, devices and components. The pair of resistive networks is configured to generate an output current signal from the two amplifier devices while facilitating a substantially identical capacitive loading on the two amplifier devices.

Abstract: A digital TV receiver includes an A/D converter converting an analog signal into a digital signal, a carrier recovery converting the digital pass-band signal into a digital base-band signal, and a symbol clock recovery converting digital real/imaginary base-band component signals into OQAM type of real/imaginary component signals, detecting timing error information by performing high pass-band filtering on the OQAM real/imaginary signals, and squaring and adding the filtered value, and for generating and outputting at least two times the frequency of the symbol clock corrected from the detected timing error information.

Abstract: A method and apparatus for receiving and processing a DS-CDMA signal in accordance with a two-stage process. The first stage comprises signal detection and employs a correlation between the sampled incoming waveform and a pseudo-noise code sequence. This stage is performed in real-time. Once a signal has been detected, a burst of the sampled incoming waveform is collected and then post-processed to recover the incoming information. The method may be implemented at low-cost on a general-purpose digital signal processor. The invention is especially suitable for DS CDMA location systems, where low-cost and low power consumption are desirable.

Abstract: Logic circuit generating four binary outputs as four threshold functions of four binary inputs, including: first, second, third, and fourth threshold functions which are respectively high if at least one, two, three and all of the binary inputs are high; first logic having two logic parts that each include NOR and NAND gates, and having two first-level inputs for receiving the binary inputs and two first-level outputs; and second logic having four second-level outputs, four second-level inputs for receiving second-level binary inputs and connected to the four first-level outputs, NAND gate, first gate generating logical OR combinations and NAND combining the logical OR combination with two other second-level binary inputs, a second gate generating logical OR combinations of two pairs of second-level binary inputs and NAND combining the logical OR combinations, and a NOR gate; wherein one of four binary outputs is generated at each of the four outputs.

Abstract: An approach for performing synchronization is provided. Phase and timing offsets are first estimated in order to calculate a frequency offset. A receiver processes a signal received from a satellite and determine offset information. The receiver includes a phase estimator for estimating a phase offset of the received signal, a timing estimator for estimating a timing offset of the received signal, and a frequency estimator for deriving a frequency offset from the phase and timing offset. A determination is made as to whether the sampling was done at a peak wave point of the data.

Abstract: A differential data transmission system that transmits encoded data symbols as differential signals. A signal for transmitting symbols on a set of at least three parallel channels, each channel having a first terminal, P1 to PN, and each channel having a second terminal connected to a common node Z. The signal comprising for each symbol an active signal on two of those channels and an inactive signal on the remaining channel or channels, the symbols being distinguishable by which two of the channels have the active signals.

Abstract: Systems and methods for determining offset phasors are disclosed. An offset vector is computed from a current channel impulse response and a previous channel impulse response. A first vector and a second vector are simultaneously and iteratively rotated in opposite directions to determine an offset phasor. A first vector of the pair of vectors is initialized with a constant value for its x coordinate and a zero for its y coordinate. A second vector of the pair of vectors is initialized with the x and y coordinates of the offset vector. The vectors are rotated in opposite directions using shift operations for a specific number of iterations. After the final rotation, the y coordinate of the second vector has become zero and the x and y coordinates of the first vector correspond to the sine and cosine of the angle formed by the offset vector. The cosine and sine terms form the real and imaginary parts of the offset phasor.

Abstract: An apparatus and method for determining the quality of a digital signal. The incoming digital signal is sampled with a number n of samples per defined pulse width, where N is greater than or equal to one, using clock cycles. An edge detector detects the edge position of a pulse of the sampled digital signal and a counter counts the clock cycles between at least a first edge and a second edge detected by the edge detector. A deviation detector then compares the counted clock cycles with a prestored reference-value in order to provide a deviation value as a measure for the instantaneous quality of the digital signal. The deviation value is then fed to a rework unit that outputs a value that is a measure for the quality of the digital signal.

Abstract: A spread-spectrum receiver has a high-rate path to receive multi-rate channels and a low-rate path to receive fixed-rate channels. In a wideband code division multiple access (WCDMA) embodiment, the high-rate path despreads multi-rate physical channels having a variable spreading factor and the low-rate path despreads physical channels having a fixed spreading factor. The high-rate path may have high-rate rake fingers to despread multipath components of the multi-rate channels. Each multi-rate channel may have a different spreading code allowing for multicode reception. The high-rate path may also include a high-rate rake with finger engines implemented in hardware to multiply symbols with a channel estimation, and a combiner to combine the multipath components. The low-rate path may include low-rate fingers to despread multipath components of the fixed-rate channels and a processor to generate a channel estimation and coherently combine symbols from the low-rate fingers with the channel estimation.

Abstract: An aligned clock forwarding scheme of an electronic system includes a first circuit path generating an aligned clock output signal to a subsystem and a second circuit path generating an aligned data signal to the subsystem. An external clock input serves as the source of the clock signal for the aligned clock forwarding scheme. A multiplication circuit receives the external clock input and sends multiplied clock signals to control the first and second circuit paths. The two circuit paths have the same physical characteristics so that both clock output and data signals experience the same environmental effect. There is no additional skew incurred between the clock and data signals during the data transfer between the two subsystems.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to present a first data signal and a first indicator signal in response to a first clock signal and an enable signal. The second circuit may be configured to present a second data signal and a second indicator signal in response to the first data signal, the first indicator signal and a second clock signal.

Abstract: The present invention calculates a difference between present sampling data and sampling data one data unit ahead, cumulatively adds up difference values calculated for every sampling by going back to the time point ahead by the number of samples of a cyclic prefix signal inserted into an initializing signal and confirms the position of the cyclic prefix signal from the sample number for which this cumulative value indicates a minimum value.

Abstract: One aspect of the present invention is a frequency conversion circuit having a pair of local oscillators. The local oscillators are frequency synthesizers based on an external frequency reference. The frequency conversion circuit is configured to perform a frequency conversion to an input signal equal to a frequency difference of signals from the pair of local oscillators; to generate an oscillator frequency difference signal; to generate an error signal using the oscillator frequency difference signal and an internal reference signal derived from the external frequency reference; and to adjust a phase of one of the pair of oscillators using the error signal. The above-described frequency conversion circuit embodiment essentially eliminates divider phase noise such as that generated by traditional prescalers. In addition, the use of two local oscillators provides a frequency conversion circuit capable of wide-range frequency conversion and high resolution.

Abstract: A clock divider and method is disclosed for generating an output clock signal having a frequency that is a fractional or integral multiple of a reference clock signal frequency. In one embodiment, the clock divider divides a clock signal by a first divisor in a first period and by a second divisor in a second period, where the second period following the first period. The clock divider circuit is triggered by a first edge of the clock signal and generates a first signal. A synchronizing circuit is coupled to the clock divider to generate a second signal from the first signal, the second signal being synchronized by a second edge of the clock signal, where the second edge is in a direction opposite to the first edge. A selector is coupled to the synchronizing circuit and the clock divider to generate an output signal by selecting the first signal and the second signal alternately between the first period and the second period.

Abstract: An interference cancellation apparatus and method may remove interference from a directional array combined signal that is received by an array antenna and array combined on a directivity-by-directivity basis. The apparatus and method input a plurality of array combined signals subjected to array combining on a directivity-by-directivity basis to select an array-combined signal corresponding to a path. A correlation value is detected between the selected array combined signal and a spread code. Detected correlation values are combined to generate a combined value, and the combined value is used to generate a temporarily determined value. The temporarily determined value is re-spread to generate a re-spread signal, and re-spread signals are sorted for every directivity, on a per path basis. The re-spread signals sorted for every directivity are then added to generate a replica signal.

Abstract: Potato chips having batch-fried texture and flavor characteristics are produced in a continuous process in a significantly reduced time by conveying potato slices through an initial frying region having a temperature of from about 115.degree. C. to about 155.degree. C. (about 240.degree. F. to about 310.degree. F.) and then through a final frying region having a temperature of from about 165.degree. C. to about 185.degree. C. (about 330.degree. F. to about 365.degree. F.).