Abstract: The network device may be configured to define or update a scene for controlling a zone in a certain area or location of a load control system. For example, the load control system may be installed in a residential home or building. At least one lighting control device that is configured to control a corresponding lighting load may be assigned to each of the one or more zones. The network device may be configured to display one or more graphical user interfaces that a user of the network device may interact with to define or update a scene. The network device may also be configured to display one or more graphical user interfaces that a user of the network device may interact with to define or update natural show functionality. After a scene and/or natural show have been configured, the may enabled or activated in response to a triggering event.

Abstract: A class of complex logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. At least one input to an individual multi-input majority gate is a fixed input. Other inputs are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node, which provides a majority function of the inputs. The summing node is coupled to a CMOS logic. Leakage through the capacitors is configured such that capacitors of a majority gate have substantially equal leakage, and this leakage has a I-V behavior which is symmetric. As such, reset device(s) on the summing node are not used. The non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels, which reduces the high leakage problem faced from majority gates that use linear input capacitors.

Abstract: A non-volatile Boolean logic circuit based on memristors and an operation method, which performs logic operations on the input logic value P and/or the input logic value Q. The logic circuit includes: a controller, a memristor M1, a memristor M2 and a resistor. The controller sets the memristor M2 to a high resistance state before performing the logic operation. When performing the logic operation, a voltage A is applied to the memristor M1, a voltage B is applied to the memristor M2, a voltage C is applied to the resistor. The resistance state of the memristor M2 is the result of the logic operation. When a logic operation is performed on the logic value P and the logic value Q or only on the logic value Q, the controller further sets the memristor M1 to the resistance state corresponding to the logic value Q before performing the logic operation.

Abstract: Pulse-generator-based reciprocal quantum logic (RQL) bias-level sensors are fabricated on an RQL integrated circuit (IC) to sample AC or DC bias values provided to operational RQL circuitry on the RQL IC. The bias-level sensors include pulse generators having strengthened or weakened bias taps (transformer couplings to RQL AC clock resonators or DC bias lines) as compared to bias taps of Josephson transmission lines in the operational RQL circuitry, or Josephson junctions (JJs) with larger or smaller critical currents as compared to JJs in the operational RQL circuitry. Pulse generators with weakened bias taps or larger JJs can have lower limits of their operational ranges placed near an optimal bias point at the centroid of the operating region of the operational RQL circuitry. The bias-level sensors can be staged by relative strength to indicate whether a provided bias value is an improvement when varied over a range.

Abstract: The various embodiments described herein include methods, devices, and systems for operating superconducting circuitry. In one aspect, a programmable circuit includes: (1) a superconducting component arranged in a multi-dimensional array of alternating narrow and wide portions, the superconducting component having an input terminal at a first end and an output terminal at a second end opposite of the first end; and (2) control circuitry coupled to the narrow portions of the superconducting component, the control circuitry configured to transition the narrow portions between superconducting and non-superconducting states. In some implementations, the superconducting component and the control circuitry are formed on different layers of the programmable circuit.

Abstract: An inverter logic circuit includes a bipolar junction transistor and a zener diode. The zener diode is connected between the base of the bipolar junction transistor and ground (or other reference voltage). The zener diode is reverse biased such that a leakage current through the zener diode allows for sufficient current through the emitter-base terminals of the bipolar junction transistor when a voltage is applied across the emitter and base terminals of the bipolar junction transistor to turn the transistor ON in the absence of an external signal to the base. As such the bipolar junction transistor functions as a normally ON bipolar junction transistor.

Abstract: A controllable lighting device may utilize a controllable impedance circuit to conduct a load current through an LED light source. The controllable impedance circuit may be coupled in series with a first switching device, which may be rendered conductive and non-conductive via a pulse-width modulated signal to adjust an average magnitude of the load current. The controllable lighting device may further comprise a control loop circuit that includes a second switching device. The second switching device may be rendered conductive and non-conductive in coordination with the first switching device to control when a feedback signal is provided to the control loop circuit and used to control the LED light source. The control loop circuit may be characterized by a time constant that is significantly greater than an operating period of the load current.

Abstract: A class of complex logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. At least one input to an individual multi-input majority gate is a fixed input. Other inputs are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node, which provides a majority function of the inputs. The summing node is coupled to a CMOS logic. Leakage through the capacitors is configured such that capacitors of a majority gate have substantially equal leakage, and this leakage has a I-V behavior which is symmetric. As such, reset device(s) on the summing node are not used. The non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels, which reduces the high leakage problem faced from majority gates that use linear input capacitors.

Abstract: Various implementations described herein are related to a device having a level shifter that receives an input signal and reference voltages and provides level-shifted input signals based on the reference voltages. The device may have a pre-driver that receives the level-shifted input signals and reference voltages and provides gate voltages based on the reference voltages. The device may have a gate stabilizer that receives the reference voltages and provides a stabilized reference voltage based on the reference voltages. The device may have an output driver that receives the reference voltages, receives the gate voltages, receives the stabilized reference voltage and provides an output pad voltage to an input-output pad based on the reference voltages, the gate voltages and the stabilized reference voltage.

Abstract: A ternary logic circuit includes: a first inverter unit; a second inverter unit arranged in parallel with the first inverter unit; a first junction unit arranged between the first inverter unit and an output terminal and including a tunnel PN junction; and a second junction unit arranged between the second inverter unit and the output terminal and including a tunnel PN junction, wherein, when an absolute value of an input voltage applied to an input terminal is less than a first input voltage, the output terminal outputs a first output voltage, and when the absolute value of the input voltage is greater than the first input voltage and less than a second input voltage, the output terminal outputs a second output voltage, and when the absolute value of the input terminal is greater than the second input voltage, the output terminal outputs a third output voltage.

Abstract: Provided is a FPGA-based design method for equally dividing an interval, including the following steps: dividing the oscillation periods of a second pulse signal of a crystal oscillator clock of a FPGA board by the number of equally divided sampling pulses, and obtaining the remainder thereof; dividing the remainder by the number of the equally divided sampling pulses to serve as an error within each sampling interval; using a counter to count from the second pulse, and stopping the counting of the counter once whenever the error within the sampling interval, which is accumulated within the second pulse interval, is greater than or equal to the vibration period. Further provided is a FPGA-based design device for equally dividing an interval. The present application makes full use of the feature of interval equal division calculation, has high precision, and is easy to implement.

Abstract: A synchronous reset signal is generated from an asynchronous reset signal. The synchronous reset signal is output from the final-stage FF among L FFs connected in a cascade arrangement. A first error determination signal is output from the final-stage FF among M FFs connected in a cascade arrangement. Among N FFs connected in a cascade arrangement, the initial-stage FF receives the first error determination signal, and the final-stage FF outputs a second error determination signal. Based on the three outputs, the presence or absence of a fault in the circuit is determined. L, M, and N fulfil M?2, L?M+1, and M+N?L+1.

Abstract: In a general aspect, a gate is formed for a quantum processor. In some implementations, an arbitrary program is received. The arbitrary program includes a first sequence of quantum logic gates, which includes a parametric XY gate. A native gate set is identified, which includes a set of quantum logic gates associated with a quantum processing unit. A second sequence of quantum logic gates corresponding to the parametric XY gate is identified, which includes a parametric quantum logic gate. Each of the quantum logic gates in the second sequence is selected from the native gate set. A native program is generated. The native program includes a third sequence of quantum logic gates. The third sequence of quantum logic gates corresponds to the first sequence of quantum logic gates and includes the second sequence of quantum logic gates. The native program is provided for execution by the quantum processing unit.

Abstract: Rapid-data-transfer sensor arrays include a controller and a plurality of sensor integrated circuits (ICs) connected in series and configured to periodically take measurements and provide measurement data to the controller as serial data. A sensor IC includes a transducer, a shift register, a serial-data-in (SDI) pin, a serial-data-out (SDO) pin, a clock pin, and a bi-directional start/done (ST/DN) pin. The sensor IC includes a power regulation circuit configured to selectively supply power for a sleep mode and an active mode for recording data and an internal shift register. When finished with the measurement, the sensor IC is configured to provide measurement data to the shift register for transfer to the controller. The controller is configured to initiate serial transfer of data from each of the shift registers of the first plurality of sensor ICs to the controller. Examples include a 2D array.

Abstract: A method of reducing reflected Radio Frequency (RF) power in substrate processing chambers may include accessing input parameters for a processing chamber that are derived from a recipe to perform a process on a substrate. The input parameters may be provided to a model that has been trained using previous input parameters and corresponding sensor measurements for the chamber. A predicted amount of reflected RF power may be received from the model and it may be determined whether the predicted reflected RF power is optimized. The input parameters may be repeatedly adjusted and processed by the model until input parameter values are found that optimize the reflected RF power. Optimized input parameters may then be provided to the chamber to process the substrate.

Abstract: A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and/or minority gates. The majority and/or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and/or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and/or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

Abstract: An apparatus, a memory device, and a method for storing parameter codes with respect to asymmetric on-die-termination (ODT) are provided. The apparatus is connected to an external device via a signal line, and includes: an on-die termination (ODT) circuit set in a first ODT state; a plurality of signal pins, each of which is connected to the signal line; and an ODT control circuit configured to: identify whether a second ODT state of the external device corresponds to the first ODT state, and based on the apparatus being an asymmetric ODT in which the first ODT state and the second ODT state are different, provide an asymmetric ODT parameter code to the external device, and disable the ODT circuit when a signal is not transmitted through the signal line.

Abstract: A true complement dynamic circuit for combining, in particular comparing, binary data on dynamic first and second input signals to third and fourth input signals, comprising at least a 1-bit compare circuit, wherein the dynamic first and second input signals are complementary signals during an evaluation phase, wherein a logical behavior is determined by the third and fourth input signals. A method for operating a true complement dynamic circuit for combining, in particular comparing, binary data on dynamic first and second input signals to third and fourth input signals, comprising operating at least a 1-bit compare circuit, wherein the dynamic first and second input signals are complementary signals during an evaluation phase, determining a logical behavior by the third and fourth input signals.

Abstract: An electrical circuit includes a driver circuit, a receiver circuit, and a keeper circuit. The receiver circuit receives an input pulse from the driver circuit during a pre-charge phase. The receiver circuit generates an output pulse based on the input pulse during an evaluation phase. The keeper circuit maintains a charge of the output pulse until another evaluation phase, wherein the keeper circuit is adapted to the driver circuit by gating a first voltage supply of the driver circuit with a second voltage supply of the keeper circuit.

Abstract: A wireless lighting control system is provided to create a lighting pattern by remotely controlling a plurality of lighting devices according to groups, thereby improving a lighting effect. The wireless lighting control system includes a first lighting device electrically connected with a first smart device to act as a master, and a plurality of second lighting devices electrically connected with a plurality of second smart devices to act as slaves, respectively. If a group for lighting control and control pattern information according to groups are selected from the first smart device, the first lighting device transmits the control pattern information according to the groups to the second lighting devices through a wireless communication scheme. At least one of lighting units of the second lighting devices and display units of the second smart devices is controlled based on the control pattern information according to the groups.