Patents Examined by Kurtis R Bahr
  • Patent number: 10936525
    Abstract: Methods, systems, and computer programs are presented for distributing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an iNOC comprising iNOC rows and iNOC columns; a set of clusters coupled to the iNOC, each cluster comprising a vertical network access point (NAP) for iNOC column communications, a horizontal NAP for iNOC row communications, a valid signal, and programmable logic, where the vertical NAP is connected to the horizontal NAP when the valid signal is activated; and an Ethernet controller coupled to the iNOC, the Ethernet controller configurable to send Ethernet-packet segments to the vertical NAPs.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: March 2, 2021
    Assignee: Achronix Semiconductor Corporation
    Inventors: Kent Orthner, Travis Johnson, Quinn Jacobson, Sarma Jonnavithula
  • Patent number: 10931281
    Abstract: The invention relates to a floating state detection circuit of a node, comprising a first conductivity type MOS transistor (M1) connected between the node (N) and a first power supply line (Vss); and a second MOS transistor (M2) of conductivity type complementary to the first conductivity type, controlled by the node (N) and connected between the gate of the first transistor (M1) and a second supply line (Vdd). In addition, a third MOS transistor (M3) of the first conductivity type connected between the gate of the first transistor (M1) and the first supply line (Vss) may be controlled by the node (N).
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: February 23, 2021
    Assignee: SPRYNGS
    Inventors: Nicolas Pierre Delorme, Christophe Le Blanc, Daniel Saias
  • Patent number: 10930341
    Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: February 23, 2021
    Assignee: GSI Technology, Inc.
    Inventors: Lee-Lean Shu, Bob Haig, Chao-Hung Chang
  • Patent number: 10924115
    Abstract: The present application provides a level shifter comprising a first P-type transistor; a second P-type transistor; a third P-type transistor, coupled to the second P-type transistor; a fourth P-type transistor, coupled to the first P-type transistor; a first N-type transistor, coupled to the third P-type transistor; a second N-type transistor, coupled to the fourth P-type transistor; a third N-type transistor, coupled to the first N-type transistor; a fourth N-type transistor, coupled to the second N-type transistor; and an inverter, coupled between the third N-type transistor and the fourth N-type transistor, wherein an input terminal of the inverter receives an input signal of the level shifter.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: February 16, 2021
    Assignee: Shenzhen Goodix Technology Co., Ltd.
    Inventor: Muli Huang
  • Patent number: 10925130
    Abstract: A lighting fixture includes a solid-state light source and control circuitry. The control circuitry is configured to receive one or more ambient light level measurements corresponding to the amount of ambient light detected by an ambient light sensor, and determine a range of values for the one or more ambient light level measurements corresponding to a desired amount of light detected by the ambient light sensor. The control circuitry is then configured to drive the solid-state light source such that the one or more ambient light level measurements received from the ambient light sensor fall within the determined range of values.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: February 16, 2021
    Assignee: IDEAL Industries Lighting LLC
    Inventor: Daniel J. Pope
  • Patent number: 10924118
    Abstract: A positive feedback XOR/XNOR gate and a low-delay hybrid logic adder are provided. The low-delay hybrid logic adder comprises the positive feedback XOR/XNOR gate and an output circuit. The positive feedback XOR/XNOR gate comprises a first PMOS transistor and a second PMOS transistor used as pass transistors, a first NMOS transistor and a second NMOS transistor constituting a pull-down network, and a third PMOS transistor, a third NMOS transistor and a fourth NMOS transistor constituting a positive feedback loop. When an XOR logic output terminal of the positive feedback XOR/XNOR gate is pulled down below a switching threshold of an inverter formed by the third PMOS transistor and the fourth NMOS transistor, the positive feedback loop starts to operate to enable the XOR logic output terminal of the positive feedback XOR/XNOR gate to enter a pull-down phase to be pulled down to a low level to avoid threshold voltage losses.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: February 16, 2021
    Assignee: Ningbo University
    Inventors: Pengjun Wang, Shunxin Ye, Yuejun Zhang, Huihong Zhang, Xiaotian Zhang
  • Patent number: 10923473
    Abstract: A high voltage logic circuit for high voltage system application comprises a first device layer formed from a first semiconductor material and comprises a low voltage logic circuit; and a second device layer formed from a second different semiconductor material and comprising one or more components of an additional circuit for generating a high voltage logic output from a low voltage logic input from the low voltage logic circuit; wherein the first and second device layers are integrally formed.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: February 16, 2021
    Assignees: MASSACHUSETTS INSTITUTE OF TECHNOLOGY, NANYANG TECHNOLOGICAL UNIVERSITY
    Inventors: Pilsoon Choi, Chirn-Chye Boon, Li-Shiuan Peh
  • Patent number: 10916279
    Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: February 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Hoon Son, Si-Hong Kim, Chang-Kyo Lee, Jung-Hwan Choi, Kyung-Soo Ha
  • Patent number: 10913388
    Abstract: A procedure is provided for actuating at least one main headlamp of a lighting unit for a motor vehicle. An overall light distribution generated by means of at least two segments of a segmented light module is allocated to a light function. The light control switches on or switches off the light function depending on at least one electric input signal of the light control. In order to facilitate the application of an animation of a vehicle lighting for a plurality of vehicle and environmental situations, the overall light distribution of the light function is built up from a plurality of light distribution segments (a-f; a-b; a-c). Each of the light distribution segments (a-f; a-b; a-c) is generated by means of at least one segment of the segmented light module. The plurality of light distribution segments (a-f; a-b; a-c) are switched on and/or switched off by the light control in a previously determined and stored sequence.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: February 9, 2021
    Assignee: Hella GmbH & Co. KGaA
    Inventors: Andreas Krauß, Boris Kubitza
  • Patent number: 10917093
    Abstract: A memory system includes a memory device with a termination circuit providing a termination impedance for a data signal in the memory device. The device also includes a calibration circuit configured to set the termination impedance to a predetermined value. The device further includes an impedance adjustment circuit configured to adjust the termination impedance based on a feedback signal indicating a change in the termination impedance due to at least one of a change in a temperature of the memory device or a change in voltage of a voltage bus in the memory device.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Yuan He
  • Patent number: 10917095
    Abstract: A level shifting circuit includes a first inverter, a second inverter, and a third inverter which are connected in a cascade. The first inverter operates at a first power supply voltage supplied to a first power supply line, and the third inverter operates at a second power supply supplied to a second power supply line. The second inverter includes a first p-type transistor having a source connected to the first power supply line, a second p-type transistor having a source connected to the second power supply line, and a first n-type transistor having a source connected to a ground line. Each gate of the first and second p-type transistors and the first n-type transistor is connected to an output terminal of the first inverter, and each drain of the first and second p-type transistors and the first n-type transistor is connected to an input terminal of the third inverter.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: February 9, 2021
    Assignee: SOCIONEXT INC.
    Inventors: Shigeaki Kawai, Atsushi Matsuda
  • Patent number: 10912170
    Abstract: A lighting fixture includes a solid-state light source and control circuitry. The control circuitry is configured to receive one or more ambient light level measurements corresponding to the amount of ambient light detected by an ambient light sensor, and determine a range of values for the one or more ambient light level measurements corresponding to a desired amount of light detected by the ambient light sensor. The control circuitry is then configured to drive the solid-state light source such that the one or more ambient light level measurements received from the ambient light sensor fall within the determined range of values.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: February 2, 2021
    Assignee: IDEAL Industries Lighting LLC
    Inventor: Daniel J. Pope
  • Patent number: 10907798
    Abstract: A method for generating a beam of light that impinges on a target, wherein beam intensity remains substantially constant regardless of beam spot size. The method involves: providing a light source, a lens that can be moved to or between various positions, a slide having positions at which the lens may be supported, a target at which a beam is directed and a controller that communicates between an optical position feedback encoder and the light source; linking the encoder and the lens, the encoder sending a lens position signal to the controller, including an encoder translator circuit which communicates with a microprocessor that receives user inputs which characterize desired beam size at the target; generating a light source power signal to the light source so that electrical power delivered by the light source changes in response to the position of the lens.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: February 2, 2021
    Assignee: THE KIRLIN COMPANY
    Inventor: Joseph Strelchuk
  • Patent number: 10910369
    Abstract: Methods and system of generating a code are described. A device can receive a request to generate a code. The device can select a set of cells among a plurality of cells. The device can determine current through the selected cells in a forward mode. The device can determine current through the selected cells in a reverse mode. The device can determine a set of differences between the currents of the forward mode and the reverse mode. The set of differences corresponds to the set of selected cells. The device can transform the set of differences into the code. The device can output the code to respond to the request.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: February 2, 2021
    Assignee: International Business Machines Corporation
    Inventor: Kangguo Cheng
  • Patent number: 10911047
    Abstract: Certain aspects of the present disclosure generally relate to a level-shifting circuit. The level-shifting circuit generally includes a first pull-up path having at least one first diode and at least one first transistor, and a second pull-up path having at least one second diode and at least one second transistor. The level-shifting circuit may also include a first pull-down path having a third transistor and a fourth transistor, wherein the fourth transistor is coupled between the third transistor and the first diode; a second pull-down path having a fifth transistor and a sixth transistor, wherein the sixth transistor is coupled between the fifth transistor and the second diode; and an overvoltage protection circuit coupled to gates of the fourth transistor and the sixth transistor.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: February 2, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Rohit Shetty, Chiew-Guan Tan, Gregory Lynch
  • Patent number: 10911048
    Abstract: A complementary metal-oxide semiconductor (CMOS) circuit comprises an inverter, a plurality of P-type metal-oxide semiconductor (PMOS) transistors, and a plurality of N-type metal-oxide semiconductor (NMOS) transistors. The inverter receives an input signal and drives one of the plurality of PMOS transistors or the plurality of NMOS transistors. The plurality of PMOS transistors generate a pull-up signal, change a beta ratio of the CMOS circuit, and change a first trip point of the CMOS circuit to a second trip point of the CMOS circuit based on the changed beta ratio. The plurality of NMOS transistors generate a pull-down signal, change the beta ratio, and change the second trip point of the CMOS circuit to a third trip point of the CMOS circuit based on the changed beta ratio.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: February 2, 2021
    Assignee: Nuvia Inc.
    Inventor: John Yong
  • Patent number: 10910176
    Abstract: A control device configured for use in a load control system to control an external electrical load may provide simple feedback regarding the operation of the control device. For example, the control device may comprise a base portion configured to be mounted to an electrical wallbox or over a mechanical switch, and a control unit connected to the base portion. The control unit may comprise a rotation portion rotatable with respect to the base portion, an actuation portion, and a light source. The control unit may be configured to control the light source to illuminate at least an illuminated portion of the actuation portion in response to actuations of the rotation portion and the actuation portion. In addition, the control unit may provide a limit indication on the illuminated portion by blinking the illuminated portion when the electrical load has reached a limit.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: February 2, 2021
    Assignee: Lutron Technology Company LLC
    Inventors: Gregory S. Altonen, Chris Dimberg, Jason C. Killo, Matthew Knauss, Michael W. Pessina, Daniel L. Twaddell
  • Patent number: 10911049
    Abstract: Methods, systems, and devices for shifting voltage levels of electrical signals and more specifically for boosted high-speed level shifting are described. A boosted level shifter may include a driver circuit that generates a drive signal having a greater voltage swing than an input signal, and the drive signal may drive the gate of a pull-up transistor within the boosted level shifter. The lower bound of the drive signal may in some cases be a negative voltage. Driving the pull-up transistor with a drive signal having a greater voltage swing than the input signal may improve the operational speed and current-sourcing capability of the pull-up transistor, which may provide speed and efficiency benefits.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: February 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Mingdong Cui, Hari Giduturi
  • Patent number: 10904976
    Abstract: A controllable lighting device may utilize a controllable impedance circuit to conduct a load current through an LED light source. The controllable impedance circuit may be coupled in series with a first switching device, which may be rendered conductive and non-conductive via a pulse-width modulated signal to adjust an average magnitude of the load current. The controllable lighting device may further comprise a control loop circuit that includes a second switching device. The second switching device may be rendered conductive and non-conductive in coordination with the first switching device to control when a feedback signal is provided to the control loop circuit and used to control the LED light source. The control loop circuit may be characterized by a time constant that is significantly greater than an operating period of the load current.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: January 26, 2021
    Assignee: Lutron Technology Company LLC
    Inventors: Stuart W. DeJonge, Robert C. Newman, Jr.
  • Patent number: 10892760
    Abstract: An apparatus for generating an output voltage signal based on an input voltage signal. The apparatus includes a first field effect transistor (FET) including a first gate configured to receive a first gate voltage based on the input voltage signal; a second (FET) including a second gate configured to receive a second gate voltage based on the input voltage signal, wherein the first and second FETs are coupled in series between a first voltage rail and a second voltage rail, and wherein the output voltage signal is produced at an output node between the first and second FETs; and a gate overdrive circuit configured to temporarily reduce the first gate voltage during a portion of a transition of the output voltage signal from a logic low level to a logic high level.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: January 12, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Sumit Rao, Wilson Jianbo Chen, Chiew-Guan Tan