Patents Examined by Kurtis R Bahr
  • Patent number: 11509306
    Abstract: An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Greg Gruber, Chi-Lin Liu, Ming-Chang Kuo, Lee-Chung Lu, Shang-Chih Hsieh
  • Patent number: 11509308
    Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: November 22, 2022
    Assignee: Kepler Computing Inc.
    Inventors: Amrita Mathuriya, Ikenna Odinaka, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni
  • Patent number: 11502691
    Abstract: An adder uses with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are the same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals to the majority gates can be analog, digital, or a combination of them, which are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: November 15, 2022
    Assignee: Kepler Computing Inc.
    Inventors: Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Gaurav Thareja, Ramamoorthy Ramesh, Amrita Mathuriya
  • Patent number: 11499693
    Abstract: An encapsulated LED switch that incorporates a MOSFET power drivers, high current transistors, or other suitable power drivers in a PCB that attaches to the LED switch such that a low power LED switch controls the output of a high-power driver. The selected power driver PCB can be adapted to different load requirements by making simple changes. The PCB's can be interchanged to provide for a predetermined output power required for a particular application. In addition, the wire gauge size of the wires attached to the MOSFET power driver PCB can also be varied to match intended load requirements. For applications in which the LED switch is used in hostile environments, such as marine applications, the LED switch and its associated power driver PCB are encapsulated to protect the circuitry from environmental factors such as high humidity, salt water, etc.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: November 15, 2022
    Inventors: Keith Rollinson, John Paul Santana
  • Patent number: 11496135
    Abstract: A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: November 8, 2022
    Assignee: GOWIN SEMICONDUCTOR CORPORATION
    Inventors: Grant Thomas Jennings, Jinghui Zhu
  • Patent number: 11488051
    Abstract: The present disclosure relates to a compiling method (50) for converting an input quantum circuit into an output quantum circuit compliant with predetermined constraints of a quantum computer, said input quantum circuit being composed of quantum gates to be applied to a set of qubits, said quantum gates arranged successively in an execution order, wherein said method comprises, for each quantum gate of the input quantum circuit processed according to the execution order: if the processed quantum gate corresponds to an operator of a set of synthesizable operators: (S53) update the synthesizable accumulated operator to include the operator corresponding to the quantum gate, otherwise: a) (S54) synthesize a partial quantum sub-circuit partially implementing the current synthesizable accumulated operator and modify accordingly the synthesizable accumulated operator, and b) (S55) append the partial quantum sub-circuit to the output quantum circuit.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: November 1, 2022
    Assignee: BULL SAS
    Inventors: Simon Martiel, Timothée Goubault De Brugière
  • Patent number: 11484859
    Abstract: An airflow generation device having a first dielectric substrate made from a rubber elastic material, a first electrode on or near by a first surface of the first dielectric substrate, a second electrode on a second surface, and a second dielectric substrate made from a rubber elastic material covering the second electrode. It makes the airflows generated by plasma caused from partial gas near by the first surface through applied voltage into the first electrode and the second electrode, and bonding portions between the first electrode and the second electrode and the first dielectric substrate, bonding portions between the second electrode and the second dielectric substrate, and bonding portions between the first dielectric substrate and the second dielectric substrate are bonded by chemical bonds with chemically crosslinking.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: November 1, 2022
    Assignees: ASAHI RUBBER INC., TOSHIBA ENERGY SYSTEMS & SOLUTIONS CORPORATION
    Inventors: Nobuyoshi Watanabe, Hideaki Sato, Yutaka Watanabe, Kenichi Yamazaki, Masahiro Asayama, Motofumi Tanaka, Hiroyuki Yasui, Toshiki Osako
  • Patent number: 11488049
    Abstract: A hybrid quantum-classical computing method for solving optimization problems though applications of non-unitary transformations. An initial state is prepared, a transformation is applied, and the state is updated to provide an improved answer. This update procedure is iterated until convergence to an approximately optimal solution.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: November 1, 2022
    Assignee: Zapata Computing, Inc.
    Inventors: Yudong Cao, Andrei Kniazev
  • Patent number: 11489525
    Abstract: A device for synchronous serial data transmission over a differential data channel and a differential clock channel includes an interface controller having a clock generator, data controller, clock transmitter block and data receiver block. The clock generator generates a transmit clock signal which, during a data transmission cycle, includes a clock pulse train having a period. The clock generator is suitably configured such that, for data transmission cycles in a dynamic operating state in which a maximum occurring differential voltage of a differential clock signal is lower than a maximum differential voltage of the clock transmitter block, the clock generator sets a duration of a first clock phase of a first clock period of the clock pulse train to be longer than a first clock phase of following clock periods and shorter than a time duration required to reach the maximum differential voltage.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: November 1, 2022
    Assignee: DR. JOHANNES HEIDENHAIN GMBH
    Inventor: Manfred Huber
  • Patent number: 11482990
    Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: October 25, 2022
    Assignee: Kepler Computing Inc.
    Inventors: Amrita Mathuriya, Ikenna Odinaka, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni
  • Patent number: 11475930
    Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: October 18, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Hoon Son, Si-Hong Kim, Chang-Kyo Lee, Jung-Hwan Choi, Kyung-Soo Ha
  • Patent number: 11455562
    Abstract: A method of detecting cliques in a graph includes determining, based on a number of nodes in the graph, a number of qubits to be included in a quantum processor. The method includes assigning to each node in the graph, a qubit of the quantum processor. The method includes operating on the qubits with a preparation circuit to create a quantum state in the qubits that corresponds to the graph. The method includes operating on the quantum state with a random walk circuit, and measuring the qubits of the quantum processor to detect cliques in the graph. The preparation circuit comprises a plurality of single- and two-qubit operators, wherein, for each pair of adjacent nodes in the graph, an operator of the plurality of two-qubit operators acts on a pair of qubits corresponding to the pair of adjacent nodes to create the quantum state.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: September 27, 2022
    Assignee: International Business Machines Corporation
    Inventors: Tal Kachman, Lior Horesh, Giacomo Nannicini, Mark S. Squillante, John A. Gunnels, Kenneth L. Clarkson
  • Patent number: 11451229
    Abstract: A tile including circuitry for use with machine learning models, the tile including: a first computational array of cells, in which the computational array of cells is a sub-array of a larger second computational array of cells; local memory coupled to the first computational array of cells; and multiple controllable bus lines, in which a first subset of the multiple controllable bus lines include multiple general purpose controllable bus lines couplable to the local memory.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: September 20, 2022
    Assignee: Google LLC
    Inventors: Michial Allen Gunter, Charles Henry Leichner, IV, Tammo Spalink
  • Patent number: 11449384
    Abstract: Techniques for providing hardware-efficient fault-tolerant quantum operations are provided. In some aspects a cavity and an ancilla transmon are used to implement a quantum operation by encoding a logical qubit using more than two energy levels of the cavity, encoding information using more than two energy levels of the ancilla transmon, and creating an interaction between the cavity and the ancilla transmon that decouples at least one error type in the ancilla transmon from the cavity.
    Type: Grant
    Filed: January 5, 2019
    Date of Patent: September 20, 2022
    Assignee: Yale University
    Inventors: Serge Rosenblum, Philip Reinhold, Liang Jiang, Steven M. Girvin, Luigi Frunzio, Michel Devoret, Robert J. Schoelkopf, III
  • Patent number: 11443779
    Abstract: Methods, systems, and devices for drive strength calibration for multi-level signaling are described. A driver may be configured to have an initial drive strength and to drive an output pin of a transmitting device toward an intermediate voltage level of a multi-level modulation scheme, where the output pin is coupled with a receiving device via a channel. The receiving device may generate, and the transmitting device may receive, a feedback signal indicating a relationship between the resulting voltage of the channel and an value for the intermediate voltage level. The transmitting device may determine and configure the driver to use an adjusted drive strength for the intermediate voltage level based on the feedback signal. The driver may be calibrated (e.g., independently) for each intermediate voltage level of the multi-level modulation scheme. Further, the driver may be calibrated for the associated channel.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: September 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Peter Mayer, Wolfgang Anton Spirkl, Michael Dieter Richter, Martin Brox, Thomas Hein
  • Patent number: 11445584
    Abstract: The network device may be configured to define or update a scene for controlling a zone in a certain area or location of a load control system. For example, the load control system may be installed in a residential home or building. At least one lighting control device that is configured to control a corresponding lighting load may be assigned to each of the one or more zones. The network device may be configured to display one or more graphical user interfaces that a user of the network device may interact with to define or update a scene. The network device may also be configured to display one or more graphical user interfaces that a user of the network device may interact with to define or update natural show functionality. After a scene and/or natural show have been configured, the may enabled or activated in response to a triggering event.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: September 13, 2022
    Assignee: Lutron Technology Company LLC
    Inventors: Bryan Robert Barnes, Shilpa Sarode, Shenchi Tian, Kenneth Priester, Brad Michael Kreschollek
  • Patent number: 11436399
    Abstract: A method for implementing a multiplier on a programmable logic device (PLD) is disclosed. Partial product bits of the multiplier are identified and how the partial product bits are to be summed to generate a final product from a multiplier and multiplicand are determined. Chains of PLD cells and cells in the chains of PLD cells for generating and summing the partial product bits are assigned. It is determined whether a bit in an assigned cell in an assigned chain of PLD cells is under-utilized. In response to determining that a bit is under-utilized, the assigning of the chains of PLD cells and cells for generating and summing the partial product bits are changed to improve an overall utilization of the chains of PLD cells and cells in the chains of PLD cells.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: September 6, 2022
    Assignee: Intel Corporation
    Inventors: Martin Langhammer, Sergey Gribok, Gregg William Baeckler
  • Patent number: 11437995
    Abstract: A quantum computing system implementing surface code in a measurement circuit may be configured to translate a quantum algorithm including at least one Hadamard gate into an equivalent circuit that lacks a Hadamard gate, the circuit including Hadamard-conjugated Pauli measurements that include joint logical measurements implemented on diagonally-arranged patches of the surface code.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: September 6, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jeongwan Haah, Michael Beverland, Nicolas Guillaume Delfosse
  • Patent number: 11418175
    Abstract: The present disclosure relates to a reciprocal quantum logic (RQL) inverter including an inverter bias tap, a pulse generating Josephson junction (JJ), and a superconducting quantum interference device (SQUID) based structure, which includes a SQUID JJ and is connected between the inverter bias tap and the pulse generating JJ. The SQUID based structure is configured to receive an inverter bias signal from the inverter bias tap and receive a data input from a previous circuit stage. When the data input is at logic state “0,” the pulse generating JJ can be triggered so as to provide an output signal with logic state “1.” When the data input is at logic state “1,” the first SQUID JJ can be triggered thereby preventing the pulse generating JJ from be triggered, such that the output signal is provided at logic state “0.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: August 16, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Stephen E. Liles, Kirti N. Bhanushali, John R. Bordelon
  • Patent number: 11411000
    Abstract: A high voltage logic circuit for high voltage system application comprises a first device layer formed from a first semiconductor material and comprises a low voltage logic circuit; and a second device layer formed from a second different semiconductor material and comprising one or more components of an additional circuit for generating a high voltage logic output from a low voltage logic input from the low voltage logic circuit; wherein the first and second device layers are integrally formed.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: August 9, 2022
    Assignees: MASSACHUSETTS INSTITUTE OF TECHNOLOGY, NANYANG TECHNOLOGICAL UNIVERSITY
    Inventors: Pilsoon Choi, Chirn-Chye Boon, Li-Shiuan Peh