Abstract: An apparatus, a memory device, and a method for storing parameter codes with respect to asymmetric on-die-termination (ODT) are provided. The apparatus is connected to an external device via a signal line, and includes: an on-die termination (ODT) circuit set in a first ODT state; a plurality of signal pins, each of which is connected to the signal line; and an ODT control circuit configured to: identify whether a second ODT state of the external device corresponds to the first ODT state, and based on the apparatus being an asymmetric ODT in which the first ODT state and the second ODT state are different, provide an asymmetric ODT parameter code to the external device, and disable the ODT circuit when a signal is not transmitted through the signal line.

Abstract: A memory system may include a memory device and a memory controller. The memory device may be configured to store data. The memory controller may be configured to communicate with the memory device by an input/output driving circuit. The input/output driving circuit comprises a pull-down driver and a gate control logic. The pull-down driver may include a first transistor and a second transistor which are electrically coupled between a pad and a ground node. The gate control logic including a third transistor and a fourth transistor which are electrically coupled between the pad and a first terminal receiving a first driving voltage, the gate control logic being configured to receive a pad voltage provided from the pad and generate a feedback voltage. The source voltage level of the second transistor is controlled by a control signal generated based on a clock signal and an enable signal.

Abstract: Aspects of the present disclosure provide techniques and apparatus for transferring data, such as between power domains via a first in, first out (FIFO) queue. An example method of transferring data includes selecting, via a source multiplexer, a first memory location included in a FIFO queue and storing first data, where the source multiplexer and the FIFO queue are in a first power domain; outputting the first data to a first level shifter; calculating, in the first power domain, a first value based on the first data; outputting the first value to a second level shifter; selecting, via at least one destination multiplexer included in a second power domain, the first level shifter and the second level shifter; calculating, in the second power domain, a second value based on the first data; and comparing the first value to the second value to generate a result.

Abstract: An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.

Abstract: In one or more implementations, a data processing device and a data processing method are disclosed that includes a data communication port configured to transmit and receive data to and from at least one computing device. Further, a replicator is included that is configured to replicate ingress data received from the data communication port to a pattern matcher and a field programmable gate array. The pattern matcher is configured to receive the replicated data directly from the replicator and to generate and transmit a trigger signal to the field programmable gate array. Still further, the field programmable gate array is configured to receive the replicated data from the replicator and the trigger signal from the pattern matcher and to perform bit operations on the replicated data as a function of the trigger signal.

Abstract: The present disclosure is directed to 3-D stacked architecture for Programmable Fabrics and Central Processing Units (CPUs). The 3-D stacked orientation enables reconfigurability of the fabric, and allows the fabric to function using coarse-grained and fine-grained acceleration for offloading CPU processing. Additionally, the programmable fabric may be able to function to interface with multiple other compute chiplet components in the 3-D stacked orientation. This enables multiple compute components to communicate without the need for offloading the data communications between the compute chiplets.

Abstract: Described are memory systems and devices in which each memory die in a three-dimensional stack of memory dies includes drive and receive circuitry that can communicate data signals from the stack on behalf of all the memory dies in the stack. The drive and receive circuitry, if defective on one device in the stack, can be disabled and substituted with the drive and receive circuitry from another. The stack of memory dies can thus function despite a failure of drive or receive circuitry in one or more of the memory dies. Each memory die includes test circuitry to detect defective drive and receive circuitry.

Abstract: A low power adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. The adder may include minority gates and/or majority gates. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

Abstract: The present invention provides a common-mode transient suppression protection circuit for a digital isolator, including a modulation circuit, a demodulation circuit and an isolation capacitor connected between the modulation circuit and the demodulation circuit. The modulation circuit includes a modulation circuit front-end and a drive circuit, which are connected in sequence, and a clamping module is arranged in the drive circuit. The protection circuit further includes a linear voltage regulator structure connected with the drive circuit, and a power supply clamp is arranged in the linear voltage regulator structure. By providing the linear voltage regulator structure having the power supply clamp and the drive circuit having the clamping module in the protection circuit, low-voltage devices in the drive circuit can be protected from being damaged by high-voltage signals generated by common-mode transient interference.

Abstract: Disclosed is an inverter which includes a first P-MOS transistor connected between a node receiving a drain voltage and a first path node and operated based on an input voltage, a first N-MOS transistor connected between the first path node and an output terminal outputting an output voltage and operated based on the drain voltage, a second P-MOS transistor connected between the output terminal and a second path node and operated based on a ground voltage, a second N-MOS transistor connected between the second path node and a node receiving the ground voltage and operated based on the input voltage, a third P-MOS transistor connected between the first path node and the second path node and operated based on the input voltage, and a third N-MOS transistor connected between the first path node and the second path node and operated based on the input voltage.

Abstract: An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.

Abstract: A low power adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. The adder may include minority gates and/or majority gates. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

Abstract: A main board, a hot plug control signal generator, and a control signal generating method thereof are provided. The hot plug control signal generator includes a controller and a latch. The controller provides a control signal. The latch is operated based on an operation power to generate a hot plug control signal. The latch sets the hot plug control signal to a disabled first logic value, and latches the hot plug control signal at the first logic value.

Abstract: A digital signal processing (DSP) block includes a Fast Fourier Transform (FFT) unit capable of performing an FFT operation. The FFT unit includes a first FFT engine capable of converting a signal between a time-domain and a frequency-domain and the first FFT engine is a fixed size FFT engine. The FFT unit also includes a second FFT engine communicatively coupled to the first FFT engine and the second FFT engine is a variable size FFT engine. The FFT unit also includes a scale/offset block communicatively coupled to the second FFT engine and the scale/offset block is capable of performing a multiplication operation, an addition operation, or a combination thereof on an output of the second FFT engine.

Abstract: The invention introduces an apparatus and a method for expanding round keys during data encryption. The method includes: configuring a word-processing circuitry to operate in a first mode to calculate a first intermediate calculation result corresponding to an even-number round key according to a last double word of a 0th double word to a 7th double word in each even-number clock cycle starting from a 2nd clock cycle; and configuring the word-processing circuitry to operate in a second mode to calculate a second intermediate calculation result corresponding to an odd-number round key according to the last double word of the 0th double word to the 7th double word in each odd-number clock cycle starting from a 3rd clock cycle. In the first mode, a first data path is formed in the word-processing circuitry, which includes a word split circuitry, a rotate-word circuitry, a substitute-word circuitry, a round-constant circuitry and a word concatenation circuitry.

Abstract: The various embodiments described herein include methods, devices, and systems for operating superconducting circuitry. In one aspect, a programmable circuit includes a configurable superconducting component and control circuitry coupled to the configurable superconducting component. The superconducting component includes an input terminal, an output terminal, and a plurality of gate terminals. The control circuitry is coupled to the superconducting component via the plurality of gate terminals. The control circuitry is adapted to selectively transition portions of the superconducting component from a superconducting state to a non-superconducting state. The control circuitry is configured to operate the superconducting component in a first configuration in which the programmable circuit is configured to perform a first function.

Abstract: A method and apparatus for an indoor horticultural system that utilizes a wired network to control lighting. The wired interface is used to relay both analog and digital intensity control information, whereby an analog signal is used to control the intensity of all LED arrays in each lighting fixture during a first mode of operation and a digital signal is used to control the intensity of each individual LED array in each lighting fixture in a second mode of operation. Both the analog and digital signals utilize the same physical interface.

Abstract: An integrated circuit includes a logic circuit comprising a plurality of logic transistors, the logic circuit comprising a plurality of logic gate lines extending in a first direction; and a power gating circuit comprising a plurality of power gating transistors, the power gating circuit comprising a first power gate line extending in a second direction that is perpendicular to the first direction, and the power gating circuit being connected to the logic circuit, wherein a plurality of source regions respectively included in the plurality of power gating transistors are connected to each other, or a plurality of drain regions respectively included in the plurality of power gating transistors are connected to each other.

Abstract: In some aspects of the present disclosure, a circuit in a first power domain is disclosed. In some aspects, the circuit in a first power domain includes a first enable-controlled logic gate coupled to a second circuit in a second power domain different from the first power domain. In some aspects, the circuit in a first power domain includes a feedback loop coupled to the first enable-controlled logic gate, the feedback loop including a first inverter and a second enable-controlled logic gate coupled to the first inverter. In some aspects, the circuit in a first power domain includes a second inverter coupled to the feedback loop.

Abstract: A detection circuit includes a tunable delay circuit that generates a delayed signal and that receives a supply voltage. The detection circuit includes a control circuit that adjusts a delay provided by the tunable delay circuit to the delayed signal. The detection circuit includes a time-to-digital converter circuit that converts the delay provided by the tunable delay circuit to the delayed signal to a digital code and adjusts the digital code based on changes in the supply voltage. The control circuit causes the tunable delay circuit to maintain the delay provided to the delayed signal constant in response to the digital code reaching an alignment value. The detection circuit may continuously monitor timing margin of a data signal relative to a clock signal and update the digital code in every clock cycle. The detection circuit may be a security sensor that detects changes in the supply voltage.