Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.

Abstract: A planar flexible electrode arrangement for a dielectric barrier plasma discharge has a central region (107) and an edge region (108) and at least one planar electrode (102) to which a high-voltage potential can be applied and which is embedded in a planar dielectric (101) that forms an upper face (103) and a contact face (104), wherein the planar dielectric (101), at least in the edge region (108), has the shape of a spiral-shaped wound-up strip (109) and the at least one electrode (102) is formed by at least one electrical conductor (114) that extends in the longitudinal direction of the wound-up strip (109) and that opens into an end face of the strip (109), which conductor (114) is surrounded, with the sole exception of the end face of the strip (109), by the dielectric of the strip (109) and, in the region of the end face of the strip (109), is electrically insulated from the surroundings by a cover element (116).

Abstract: The various embodiments described herein include methods, devices, and systems for operating superconducting circuitry. In one aspect, a programmable circuit includes: (1) a superconducting component arranged in a multi-dimensional array of alternating narrow and wide portions, the superconducting component having an input terminal at a first end and an output terminal at a second end opposite of the first end; and (2) control circuitry coupled to the narrow portions of the superconducting component, the control circuitry configured to transition the narrow portions between superconducting and non-superconducting states. In some implementations, the superconducting component and the control circuitry are formed on different layers of the programmable circuit.

Abstract: A hybrid computing system for solving a computational problem includes a digital processor, a quantum processor having qubits and coupling devices that together define a working graph of the quantum processor, and at least one nontransitory processor-readable medium communicatively coupleable to the digital processor which stores at least one of processor-executable instructions or data. The digital processor receives a computational problem, and programs the quantum processor with a first set of bias fields and a first set of coupling strengths. The quantum processor generates samples as potential solutions to an approximation of the problem. The digital processor updates the approximation by determining a second set of bias fields based at least in part on the first set of bias fields and a first set of mean fields that are based at least in part on the first set of samples and coupling strengths of one or more virtual coupling devices.

Abstract: An input circuit includes an input buffer circuit using a first node as an input and a second node as an output, an N-type transistor having a source coupled to the input terminal, a drain coupled to the first node, and a gate coupled to a power supply, and a pull-up circuit provided between the first node and the power supply. The pull-up circuit is configured to make the power supply and the first node conducive with each other for a predetermined period when the input signal transitions from low to high and not to make the power supply and the first node conductive with each other when the input signal transitions from high to low.

Abstract: A method of reducing reflected Radio Frequency (RF) power in substrate processing chambers may include accessing input parameters for a processing chamber that are derived from a recipe to perform a process on a substrate. The input parameters may be provided to a model that has been trained using previous input parameters and corresponding sensor measurements for the chamber. A predicted amount of reflected RF power may be received from the model and it may be determined whether the predicted reflected RF power is optimized. The input parameters may be repeatedly adjusted and processed by the model until input parameter values are found that optimize the reflected RF power. Optimized input parameters may then be provided to the chamber to process the substrate.

Abstract: A quantum computer includes: a setting unit configured to set a parameter group of n layers based on each coefficient in a linear sum of unitary operators whose number is 2 to the n-th power, wherein the parameter group of k-th (2?k?n) layer is recursively set based on the parameter group of (k?1)-th layer; a quantum gate having n+m qubits including n auxiliary qubits and m target qubits, and configured to execute a predetermined calculation on an input value input to each qubit based the parameter group of n layers; and a specification unit configured to specify the linear sum of the unitary operators based on a calculation result of the quantum gate.

Abstract: A quantum write controller includes an in-phase path that includes a first digital to analog converter (DAC) configured to receive an in-phase signal at a first frequency, a first mixer configured to create a third in phase frequency, a first combiner configured to combine an output of the first mixer with an output of a third mixer, and a second mixer configured to mix an output of the first combiner with a fourth in phase frequency. There is a quadrature path that includes a second DAC configured to receive a quadrature phase signal at the first frequency, a third mixer configured to create a third quadrature frequency, a second combiner configured to combine the output of the third mixer with the output of the first mixer, and a fourth mixer configured to mix an output of the second combiner with a fourth quadrature frequency.

Abstract: In a general aspect, a gate is formed for a quantum processor. In some implementations, an arbitrary program is received. The arbitrary program includes a first sequence of quantum logic gates, which includes a parametric XY gate. A native gate set is identified, which includes a set of quantum logic gates associated with a quantum processing unit. A second sequence of quantum logic gates corresponding to the parametric XY gate is identified, which includes a parametric quantum logic gate. Each of the quantum logic gates in the second sequence is selected from the native gate set. A native program is generated. The native program includes a third sequence of quantum logic gates. The third sequence of quantum logic gates corresponds to the first sequence of quantum logic gates and includes the second sequence of quantum logic gates. The native program is provided for execution by the quantum processing unit.

Abstract: A method of generating a randomized benchmarking protocol includes providing a randomly generated plurality of Hadamard gates; applying the Hadamard gates to a plurality of qubits; and generating randomly a plurality of Hadamard-free Clifford circuits. Each of the plurality of Hadamard-free Clifford circuits is generated by at least randomly generating a uniformly distributed phase (P) gate, and randomly generating a uniformly distributed linear Boolean invertible matrix of conditional NOT (CNOT) gate, and combining the P and CNOT gates to form each of the plurality of Hadamard-free Clifford circuits. The method also includes combining each of the plurality of Hadamard-free Clifford circuits with corresponding each of the plurality of Hadamard gates to form a sequence of alternating Hadamard-free Clifford-Hadamard pairs circuit to form the randomized benchmarking protocol; and measuring noise in a quantum mechanical processor using the randomized benchmarking protocol.

Abstract: A light fixture includes a communication input and output, a plurality of LED lights, an LED driver, first and second control modules, and a feedback circuit. The communication input is configured to receive a control signal. The communication output is configured to relay the control signal to a downstream light fixture. The LED driver is electrically coupled with the plurality of LED lights. The first control module is in signal communication with the communication input and output and the LED driver and is configured to transmit a driver signal to the LED driver that controls operation of the plurality of LED lights. The second control module is in signal communication with the first control module. The feedback circuit is in signal communication with the second control module and the LED driver. The LED driver transmits a feedback signal to the second control module via the feedback circuit.

Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.

Abstract: Methods, systems and apparatus for producing quantum circuits with low T gate counts. In one aspect, a method for performing a temporary logical AND operation on two control qubits includes the actions of obtaining an ancilla qubit in an A-state; computing a logical-AND of the two control qubits and storing the computed logical-AND in the state of the ancilla qubit, comprising replacing the A-state of the ancilla qubit with the logical-AND of the two control qubits; maintaining the ancilla qubit storing the logical-AND of the two controls until a first condition is satisfied; and erasing the ancilla qubit when the first condition is satisfied.

Abstract: Main wiring including a plurality of differential transmission lines for transmitting differential signals is formed on a motherboard. Termination resistors, provided at both ends of each of the plurality of differential transmission lines, connect the plurality of differential transmission lines to each other. A plurality of daughter boards are connected in parallel to each other via the main wiring. A line characteristic impedance of each differential transmission line is higher than a termination resistance value, which is a resistance value of the termination resistor.

Abstract: None of the existing quantum programming languages provide specialized support for programming patterns such as conditional-adjoint or adjoint-via-conjugation. As a result, compilers of these languages fail to exploit the optimization opportunities mentioned in this disclosure. Further, none of the available quantum programming languages provide support for automatic translation of circuits using clean qubits to circuits that use idle qubits. Thus, the resulting circuits oftentimes use more qubits than would be required. Embodiments of the disclosed technology, thus allow one to run said circuits on smaller quantum devices. Previous multiplication circuits make use of (expensive) controlled additions. Embodiments of the disclosed technology employ multipliers that work using conditional-adjoint additions, which are cheaper to implement on both near-term and large-scale quantum hardware. The savings lie between 1.5 and 2× in circuit depth for large number of qubits.

Abstract: A circuit includes a plurality of first counting gates, a first ternary half adder (THA) and a second THA that are connected to the plurality of first counting gates, a third THA configured to receive a sum output signal of the first THA and a sum output signal of the second THA, a first ternary sum gate configured to receive a carry output signal of the first THA and a carry output signal of the second THA, and a second ternary sum gate configured to receive a carry output signal of the third THA and an output signal of the first ternary sum gate, wherein the third THA and the second ternary sum gate may be configured to output voltage signals corresponding to a number of drain voltages among input signals applied to the plurality of first counting gates.

Abstract: A light-emitting circuit includes first and second light-emitting element strings respectively configured to emit light having a first and second color temperatures; a rectifying circuit configured to rectify a voltage, input by an alternating current (AC) power source, to generate a driving voltage; a string switching circuit configured to select at least one light-emitting element string to be used for light emission from among the first light-emitting element string and the second light-emitting element string; an off/on sensing circuit configured to change a selection of the string switching circuit to change a color temperature of light, which is emitted by the light-emitting circuit, when the AC power source is turned off and then turned on; and a driving circuit configured to turn on, in turn, light-emitting elements in the selected at least one light-emitting element string, according to a change in the driving voltage over time.

Abstract: A Bias Unit Element (UE) has a digital input and sign input, and comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.

Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.

Abstract: An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.