Abstract: A method and system for simulating a chronic disease condition comprises a compact, easy to use electronic device. A virtual pet device for providing at least one disease control parameter value and a general health status value for the virtual pet having a chronic medical condition includes: a microprocessor having a memory, a housing, an input unit external to the housing, and a display integral with the housing. The device may include a plurality of icons and a plurality of input buttons for inputting medical regimen-related data into the device. Graphics are provided for portraying a plurality of stages in the development and maturation of the virtual pet, as well as for displaying at least one disease control parameter. An audio unit provides sound synchronized to the graphics, and includes an alarm function related to scheduled medication administration.

Abstract: A method and apparatus for managing simulation results involve identifying errors within a group of simulation results so that the errors can be recorded into a database and viewed for analysis. In a preferred embodiment of the invention, distinct transactions within a group of simulation results are identified and recorded along with the identified errors. Recorded error-specific data and transaction-specific data are then utilized to graphically display the simulation results such that individual transactions identified within the simulation results are graphically distinct and such that errors occurring during a transaction are visually identified with the transaction. Recording and displaying error information and raising the level of abstraction of simulation results from cycles and signals to transactions enables easier simulation analysis and debugging.

Abstract: Improvements are made to an electronic circuit simulator. The circuit is represented by a set of nodes to which devices and components are connected. In a computer simulator of circuit behavior using the Harmonic Balancing methodology it is desirable to precondition the Jacobian matrix associated with the circuit equations. Proper preconditioning of the Jacobian matrix may increase the computational efficiency of the simulator. A preconditioning matrix for the Jacobian matrix may be obtained by generating an inverse matrix for dissimilar diagonal blocks.

Abstract: In a method of estimating the lifetime of a floating SOI-MOSFET, constants A and B, stress condition dependency Id.sup.t (S) of a drain current and stress condition dependency Isub(S) of a substrate current in a body-fixed SOI-MOSFET, and stress condition dependency Id.sup.f (S) of a drain current in the floating SOI-MOSFET are obtained from experiment to estimate lifetime .tau..sup.f (S) from the following equation: ##EQU1## where W.sup.f represents a known channel width of the floating SOI-MOSFET.

Abstract: An instruction emulation system translates target instructions into emulation instructions for execution by a host processor. A jump table has pointer entries employed to locate, in a translation instruction memory, sets of translating instructions for generating emulation instructions executable by the host for each of the differing types of target instructions. In one embodiment, each of pointer entries in the jump table has an entry length which is no greater than the shortest target instruction length, thereby enabling the jump table to handle target instructions of non-uniform instruction length. For another embodiment in which the target instructions comprise blocks of target instructions, including signal-handling target instructions, the jump table is augmented by a jump table shadow memory which saves memory requirements for code complication. In another embodiment, the jump table memory is partitioned into segments corresponding to the blocks stored in the target instruction memory.

Abstract: A computer implemented method for simulating a resistive circuit, including a plurality of macro circuits that are arranged hierarchically. The method includes the steps of reading a netlist description of the resistive circuit and recursively traversing the resistive circuit starting from terminal nodes of a macro circuit at a highest level of hierarchy using precharacterizations of each of the plurality of macro circuits to determine node voltages and branch currents of the resistive circuit.

Abstract: A method of implementing a boundary scan chain is provided using a programmable IC that includes dedicated boundary scan logic having a programmable boundary scan bit-order. Boundary scan cells are provided, each cell being capable of providing the boundary scan functions associated with one I/O pad. In a mask programmable device, dedicated tracks are provided for adding mask programmable interconnect lines. In other programmable ICs such as FPGAs or PLDs, programmable interconnect lines are provided. In either case, the interconnect lines are used to implement the boundary scan data chain. Using these lines, the programmed device can "swap the order" of I/O cells in the boundary scan data chain, or leave cells out of the chain entirely. In one embodiment, the interconnect lines traverse each cell, programmably connecting the data inputs and outputs of adjacent or non-adjacent boundary scan cells.

Abstract: A method and apparatus for designing and editing a distribution system for a building is disclosed. Elements of such distribution systems and requirements of relevant standard, are stored in a computer's memory. Building parameters are entered into a computer manually. The user identify the standard to be followed and the element to be optimized. The system divides the building into sections as appropriate to the user identified standard. The system then computes layout needed to comply with the selected standard. The layout is routed and sized to avoid building structural members, yet the elements of the layout are optimized for size and length. The apparatus prints out a hard copy of the design layout which can include an elements listing needed to complete the system. The design layout as well as the building parameters can be edited. The edited layout is checked for compliance with the identified standard as well as avoidance of building parameters.

Abstract: A computer system for providing user control of multimedia output parameters. The computer system includes a central processing unit (CPU) coupled to a memory unit. The memory unit includes a system management mode (SMM) memory and a main memory. The SMM memory is not mapped as part of the main memory and includes a prestored interrupt processing program. The interrupt processing program includes multimedia parameter control functions that provide a user with control of the output of multimedia parameters. The computer system further includes an input means for a user to generate multimedia parameter control requests, and an interrupt triggering means for detecting the multimedia parameter control request and in response issues an interrupt to the CPU. In response to the interrupt, the CPU interrupts execution, stores the current system state data of the computer system into the SMM memory, and starts execution of the interrupt processing program to service the multimedia parameter control functions.

Abstract: Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that placement of the cell and the wire routine be done correctly to avoid any congestion of wires. Placement of the cells and the routing of the wires to avoid congestion can be accomplished by determining congestion of various regions, or pieces, of the IC's after an initial placement of the cells and routing of the wires. The present invention discloses a method and apparatus to define the regions, or pieces, of the IC, determine various density measurement of the pieces, and adjust the sizes of the pieces to reduce congestion of congested pieces by reallocating space from uncongested pieces to congested pieces.

Abstract: A universal storage management system which facilitates storage of data from a client computer and computer network is disclosed. The universal storage management system functions as an interface between the client computer and at least one storage device, and facilitates reading and writing of data by handling I/O operations. I/O operation overhead in the client computer is reduced by translating I/O commands from the client computer into high level commands which are employed by the storage management system to carry out I/O operations. The storage management system also enables interconnection of a normally incompatible storage device and client computer by translating I/O requests into an intermediate common format which is employed to generate commands which are compatible with the storage device receiving the request. Files, error messages and other information from the storage device are similarly translated and provided to the client computer.

Abstract: Operation cycles to be subjected to an IDDQ test are selected from among operation cycles defined by a test pattern for a functional test of a CMOS integrated circuit so that a sufficient and necessary number of operation cycles are accurately and rapidly selected. A combination of sets of m-bit data are selected so that the combination includes sets of m-bit data each bit of which is changed from one of the values "0" and "1" to the other at least once. The operation cycles corresponding to the sets of m-bit data included in the combination are rendered to be the IDDQ test cycles to be subjected to the IDDQ test.

Abstract: The invention provides a system and a method for managing digital data in a computer peripheral device which receives the data from a host computer. The system includes a processing circuit which receives data from the host and uses the data to control the computer peripheral device. The system further includes a memory device which stores data and comprises a plurality of storage locations. The system still further includes a memory management unit for controlling the storage of data in the memory device. The system still further includes a compression program for effecting compressed storage of data in memory. The memory management unit determines when the amount of data stored in the memory device exceeds a predetermined threshold and generates a compression signal. The compression program responds to the compression signal by effecting compressed storage of data.

Abstract: An interactive method and system for designing a door system for an automotive vehicle without the necessity of building a prototype is disclosed. Initially, a door system design is selected and a set of door system data describing attributes of a door structure, a door opening panel (DOP), mating surfaces of the DOP and the vehicle, vehicle attributes, hardware attributes, and seal system attributes are generated based on the selected design. A door system model is then generated from the door system data, and a design criteria for the door system is selected. Door system performance is then determined using predetermined conditions based upon the door system model by computing and displaying time histories of predefined parameters of the door system, door related hardware, and vehicle passenger compartment.

Abstract: Damped structures with isolators such as, for example, total vehicles, are analyzed and automatically optimized using a model representing the structure, the model possibly consisting of both rigid and flexible components, together with initial values for isolator design variables, a set of design constraints, and an optimization criterion. Each isolator may have frequency dependent or frequency independent parameters. Excitations may come from a combination of internal and external sources that may be expressed as deterministic or random functions. Finite element modeling is used to determine eigenvectors of flexible finite element components. A total system model is obtained using the rigid component parameters, eigenvectors of flexible components, and spring-damping parameters of isolators. Vibration analysis using the total system model yields system frequency responses and an optimization function.

Abstract: An apparatus is programmed with a plurality of programming instructions for automatically generating a reconfiguration script comprising a plurality of configuration commands for reconfiguring a plurality of telecommunication devices of a telecommunication system, based on a current and a target descriptive image of the telecommunication system. The current descriptive image specifies the devices and their features included in the current configuration of the telecommunication system, whereas the target image specifies the devices and their features to be included in the target configuration of the telecommunication system. The plurality of programming instructions generate the reconfiguration script employing feature dependency graph (FDG) data structures, a device model modeling the rules and behaviors of the telecommunication devices, and feature deletion/addition linklists.

Abstract: In a computerized method for predicting a particular user preference for an item based on observations made about the item by other users, client computers are used to enter the observations about the items. The observations are forwarded to a server computer via a network. The observations are collected in a database of the server computer. Using factor analysis, a solver module of the server computer analyzes the observations to generate a model of the observations. The models are distributed to the client computers via the network. The client computer makes predictions of preferences of the particular user using the models.

Abstract: A CPU of the RISC type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes limited to register-to-register operations and register load/store operations. Byte manipulation instructions include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

Abstract: There is disclosed a multi-processor system and method arranged, in one embodiment, as an image and graphics processor. The image processor is structured with several individual processors all having communication links to several memories. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.

Abstract: Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that placement of the cell and the wire routine be done correctly to avoid any congestion of wires. The present invention discloses method and apparatus to reduce or to eliminate cell placement and wire routing congestion. The congestion reduction is achieved by first examining regions of the IC to determine whether horizontal or vertical congestion exists. If horizontal congestion exists, then the cells are moved, within the columns, vertically to give more room for the cells and in between the cells for the routing of the wires. If vertical congestion exists, then the cells are moved to different columns to alleviate congestion.