Abstract: An apparatus and method for communicating characteristics about a memory module to a processor unit. A method and apparatus for communicating memory module characteristics, such as whether the module can communicate in a deterministic mode, memory size, memory speed, memory type and whether the memory is cachable to a processor. In the present invention, the processor asserts a request signal onto the system bus and the memory module corresponding to the address of the request respond with information regarding its characteristics.

Abstract: A self-contained, self-configurable cascadable pipelined processor chip (160) is diclosed. The chip contains a computation section (FIGS. 1a-1d) which consists of various types of computation circuits (20-42) that can be software-interconnected in any desired configuration by a set of multiplexers (44-52) whose settings are under the control of a control section (FIG. 2 ). The control section consists of various types of control circuits (60-76) which are also software-interconnectable in any desired configuration under program control. The chip (160) is configured by a very long instruction word and then executes the algorithm defined by that configuration iteratively until stopped. The chip (160) can be programmed to reconfigure itself in response to computation results or other selectable parameters, either in accordance with internally stored configurations or in accordance with configuration information stored in an external random access memory (56, 58).

Abstract: A 64-bit wide unified integer and floating-point datapath for a RISC processor. The unified datapath allows for the sharing of some of the major hardware resources within the integer and floating-point execution units, as well as simplifying a large portion of the peripheral circuitry. The unified datapath results in a more efficient use of the hardware with reduced average power dissipation and area, without compromising the major performance advantages of RISC processors.

Abstract: A partial width stall mechanism within a register alias table unit (RAT) for handling partial width data dependencies of a given set of operations issued simultaneously within a superscalar microprocessor. Operations of the given set are presented to the RAT in program order and partial width data dependencies occur when the size of a logical source register that is presented to the RAT for renaming to a corresponding physical source register is larger than the corresponding physical source register selected by the RAT. At this occurrence, the data required by the logical source register to be renamed does not reside in any one physical source register. Therefore, renaming of that logical register must be stalled until the data for that logical register is accumulated into one location. The data will be so accumulated when the last operation to have written the physical source register is retired and is, therefore, nonspeculative.

Abstract: An interrupt controller for use in a computer system capable of utilizing multiple processors provides a system for automatically distributing interrupts among processors installed in the system. More specifically, in the present invention, each processor has a corresponding interrupt controller. In one embodiment, one interrupt controller acts as a master to acknowledge interrupts at the system level and manage the distribution of interrupts, and any other interrupt controllers act as slave interrupt controllers. The master and slave interrupt controllers also provide an interface for a processor to interrupt another processor, to transfer an interrupt to another processor and to interrupt itself under local software control. Finally, the interrupt controllers provide different masking levels that allow a corresponding processor to temporarily mask interrupts assigned to the processor.

Abstract: A computer system using virtual memory addressing and having a direct-mapped cache is operated in a manner to simulate the effect of a set associative cache by detecting cache misses and remapping pages in the main memory so that memory references which would have caused thrashing can instead coexist in the cache. Two memory addresses which are in different pages but which map to the same location in the cache may not reside in the direct-mapped cache at the same time, so alternate reference to these addresses by a task executing on the CPU would cause thrashing. However, if the location of one of these addresses in main memory is changed, the data items having these addresses can coexist in the cache, and performance will be markedly improved because thrashing will no longer result. For a CPU executing a virtual memory operating system, a page of data or instructions can be moved to a different physical page frame but remain the same virtual address.

Abstract: The data storage subsystem is implemented using an array of data storage elements which vary in data storage characteristics and/or data storage capacity. Control apparatus automatically compensates for any nonuniformity among the data storage elements by selecting a set of physical characteristics that define a common data storage element format. The selected set of physical characteristics may not match any of the disk drives but each disk drive can emulate these selected characteristics. This capability enables the disk drives in the data storage subsystem to be replaced by nonidentical disk drives in a nondisruptive manner to provide continuous data availability.

Abstract: An interface protocol between a microprocessor register file (6) and a plurality of first functional units capable of independently executing first microinstructions that take a plurality of clock cycles to complete execution. A plurality of second functional units capable of independently executing second microinstructions that take a single clock cycle to complete execution. The first and second microinstructions are issued by an instruction decoder. A microintruction bus (112) is connected to the instruction decoder, the register file, and to each of the first and second functional units. A REG interface and a destination bus (110) are also connected to the register file (6). A Scbok line (102) is connected between the instruction unit, the register file and to each one of the first and second functional units. The instruction decoder includes means for asserting the Scbok line to signal that a current microinstruction on the microintruction bus (112) is valid.

Abstract: An automatic operation control system for controlling the automatic operation of a computer system, stores in a storage unit the status informations of hardware configuration and software configuration of a computer system, a running event of the operating system and application programs, and an operation event of the computer system, and supplies a procedure for an operation command to be executed in accordance with the configuration information and the occurred event.

Abstract: A highly-parallel processing system in which a number of processing elements are interconnected by a network, and are also connected to a system bus and controlled by a central processing unit. Each processing element includes a memory, and all of the memories in the processing elements form at least part of the memory available to the CPU. The processing elements normally execute programs in MIMD mode, and the CPU or another unit can interrupt them to execute a SIMD instruction. The network allows for transmission of variable length messages and also for combining messages when received at a common processing element.

Abstract: A system that determines whether a multi-processor operation is possible without data set expansion by comparing the size of the data sets and the position of elements of the data sets, the sampling frequency of the data sets and the amount of overlap of the data sets among the processors. If all of the conditions are not met the operation cannot proceed. If the last condition only is not met, the size of the overlap necessary to allow the operation to proceed can be determined. If sufficient memory space for the expansion of the subsets by exchanging the needed elements is available, the operation can proceed after the communication of the data sets among the processors in accordance with the required expansion.

Abstract: A data processing apparatus includes a dual port data input register, first and second sequential ring counters, first and second register files, first and second data transfer circuits, a dual port data output register and N single bit processing elements. The dual port data input register has an M bit wide input port and an N bit wide output port. The first sequential ring counter cyclically selects one column of the data input register for input. The first data transfer circuit has a plurality of input segments, which are subsets of consecutive columns of the data input register. The first data transfer circuit transfers data from a selected row of the data input register to a selected row of the first register file for all columns of each input segment in a repetitive sequence of consecutive input segments in synchronism with said first sequential ring counter.

Abstract: Source operand data supplied from a register file are held in registers. The data of the registers and load data from a data memory are bypassed and supplied to a selection circuit. An execution stage includes an arithmetic and logic unit for performing an operation on the source operand data and a memory access stage includes an arithmetic and logic unit for performing an operation on data selected by the selection circuit. Selection of the selection circuit is controlled by data dependency between a load instruction and an operation instruction following the same. The output of the arithmetic and logic unit in the execution stage and the output of the arithmetic and logic unit in the memory access stage are selected in a selector according to a presence/absence of data dependency. Load data from the data memory is also supplied to the selector.

Abstract: A massively parallel computer system including a plurality of processing nodes under control of a system controller. The processing nodes are interconnected by a plurality of communications links. Each processing node comprises at least one processor, a memory, and a router node connected to the communications links for transferring in a series of message transfer cycles messages over the communications links. The controller enables each processing node to establish a message queue in its memory. The controller further enables storage of messages received by the processing nodes for their respective processors during a message transfer cycle to be stored in the message queue.

Abstract: A color measurement network message log structure is disclosed for use in controlling communications among systems such as a plurality of film processing laboratories and remotely located systems, including a remotely located host system. Each processing laboratory includes at least one film processing apparatus interconnected to a densitometer for obtaining data related to color quality during film processing procedures. Signals representative of color quality data are transmitted from the densitometer to the host system through conventional modem devices and telecommunication lines. The host system can comprise a conventional processor and interconnected printer device. The processor is responsive to signals received from the densitometer at each processing laboratory to process the color quality data represented thereby. Each of the densitometers is provided with a dual port structure for communications with the film processing apparatus and remotely located system.

Abstract: Herein disclosed is a disk controller having a cache. This cache is so managed that a predetermined part composed of at least one of a plurality parts divided therefrom is initialized. In response to a request for cache activation from a host computer, the initializations of the cache are partly executed in a repeated manner, and a request for disk input/output is intermittently processed so that the whole initializations of a cache having a large capacity can be executed in parallel with the online process.Moreover, the logic failure of the cache and the hardware failure of a memory are divided. When the logic failure occurs, the use of the case is temporarily prohibited, and the whole initializations of the cache are executed automatically at the side of the disk controller without any intervention of a maintenance man so that the cache can be used again.

Abstract: A circuit for generating programmable interrupt signals including apparatus for counting the individual rows of signals being displayed by an output display, apparatus for selectively storing a signal indicating a particular row, apparatus for determining when the signal counted by the apparatus for counting the individual rows of signals and the signal stored by the apparatus for selectively storing a signal indicating a particular row are equal, and apparatus for producing an interrupt signal when the signal counted by the apparatus for counting the individual rows of signals and the signal stored by the apparatus for selectively storing a signal indicating a particular row are equal.

Abstract: The invention is a system and method for providing a breakpoint exception at any predetermined instruction address in a processor system of the type including an integrated circuit microprocessor and an instruction cache and memory management unit (CMMU) where code addresses are sent to the instruction CMMU and the instruction CMMU returns with code instructions and returns with a FAULT code reply signal when there is no reply code, and wherein an exception is forced in the microprocessor in response to the FAULT code reply signal.

Abstract: A data processor includes a central processing unit having an execution unit, a program counter for supplying the address of the instruction to be executed and a program status word for holding the execution status of the program, an interrupt request generating means for generating the processing request in asynchronisum with the central processing unit, and interrupt controller receiving the processing request from the interrupt requested generating means and a data memory for storing the processing data. The interrupt request generating means is capable of generating a macro-service request for starting the macro-service processing while saving the contents of the program counter and the program status word. The data memory the control information for starting the macro-service processing and the command information for executing a plurality of macro-service processing. The control information includes a base address for the command information corresponding to the macro-service processing.

Abstract: A method and system for enhanced branch history prediction accuracy in a superscalar processor system by maintaining branch history tables which include a separate branch history for each instruction fetch position within a multi-instruction access. In a superscalar processor system which is capable of accessing multiple instructions simultaneously, a branch history table is established which includes a predictive field for each possible instruction fetch position within a multi-instruction access. Each group of predictive fields is accessed within the branch history table utilizing a portion of the instruction fetch address, such as the low order address bits. A particular predictive field within the group is then selected which corresponds to the position of the branch instruction within the instruction fetch. The content of the selected predictive field is then utilized to predict whether or not a branch is taken for the corresponding branch instruction.