Abstract: A method is provided for preprocessing multiple instructions prior to execution of such instructions in a digital computer having an instruction decoder, an instruction execution unit, and multiple general purpose registers which are read to produce memory addresses during the preprocessing.

Abstract: A multiple processor network with a centrally synchronized bus in which a processor desiring to be on line sends a request signal via the bus to an arbiter which generates an allocation signal.

Abstract: An instruction decoder generates implied specifiers for certain predefined instructions, and an operand processing unit preprocess most of the implied specifiers in the same fashion as express operand specifiers. For instructions having an implied autoincrement or autodecrement of the stack pointer, an implied read or write access type is assigned to the instruction and the decode logic is configured accordingly. When an opcode is decoded and is found to have an implied write specifier, a destination operand is created for autodecrementing the stack pointer. If an opcode is decoded and found to have an implied read specifier, a source operand is created for autoincrementing the stack pointer. A register or short literal specifier can be decoded simultaneously with the generation of the implied operand. Therefore some common instructions such as "PUSH Rx" can be decoded in a single cycle.

Abstract: A priority resolver shortens the time between a requesting circuit initiating a request for access to a requested circuit that is shared with other circuits and the requesting circuit actually functioning with the requested circuit. A first portion of the priority resolver circuit is associated with the requesting circuit and makes a request for access to another portion of the priority resolver circuit associated with the requested circuit before the first portion has chosen the highest priority one of a plurality of requesting circuits that have concurrently bid for access to the requested circuit. Before the portion of the priority resolver associated with the requested circuit can respond to the access request and return an access grant signal, the first portion of the priority resolver circuit has chosen the highest priority requesting circuit. In this manner the time for accessing requested circuits is decreased.

Abstract: In a processing system having a plurality of CPUs, a common storage device is shared by all the CPUs, online control programs are executed by the CPUs, and monitor programs monitor the states of the online control programs and control the online control programs. When a failure of an online control program occurs, the process of the failed online control program can be taken over by another online control program. A method of recovering from the failure of an online control program is characterized by quick restart information for each online control program which is stored separately in the common storage device and separate from a log.

Abstract: The invention relates to a bi-directional communication and control system which includes a common network line over which messages are transmitted in a specific message format and a plurality of hardware based digital IC's which are coupled to said common network line and are arranged to receive messages from and transmit messages to said network line in said specific format. Specifically, the invention concerns a multipurpose two-way communication device which is connected to one of said digital ICs, said device being operable in a master mode in which said device interfaces an external controller to said network line through said connected digital IC so that said external controller can act as the master controller for said plurality of digital ICs coupled to said common network line.

Abstract: A plurality of processors are connected to one another through a transmission line to constitute a distributed data processing system. Each processor adds a processor identification code to the time of its own and broadcasts them as time data at fixed periods. Each processor receives the time data on the transmission line, judges whether or not the received time data is the time data of the processor as the object of synchronization and sets the time data from the processor as the object of synchronization to the timer of its own system in order to synchronize the timers.

Abstract: A mechanism allows for programming the order of cells for an operator to enter data in a spreadsheet. Each cell of the spreadsheet may be provided with a "next cell" attribute, and these attributes as well as other attributes for the cells are stored in a table. The "next cell" attribute may be a constant, such as the name of the next cell, or it may be a logic expression so that the next cell to be edited can be different depending on some condition. When the operator presses the NEXT CELL key, the "next cell" attribute is searched by accessing the attribute table, and if a "next cell" attribute is found, it is evaluated to determine the next cell to be edited.

Abstract: A microprocessor system includes interstage buffer circuits and a slave system. The interstage buffer circuits include data signal buffer circuits (8a, 8b) and a swap buffer circuit (9), connected in parallel with the data signal buffer circuits (8a, 8b), for performing bit width conversion. The slave system is connected to a bus for connecting an interstage control signal buffer circuit and an interface control signal buffer circuits, a bus for connecting an interstage address signal buffer circuit and an interface address signal buffer circuit, and a bus for connecting the buffer circuits (8a, 9, 8b) and an interface data signal buffer circuit.

Abstract: A data structure format conversion system comprising a front end converter, a back end converter, and a converter executive. The front end converter converts a source data structure in a source format to data in an intermediate format. The back end converter converts the data in the intermediate format to a target data structure in a target format. Finally, a converter executive controls the front end converter and back end converter to effect a conversion from the source data structure in the source format to the target data structure in the target format, through the intermediate format.

Abstract: A computer has a pageable memory which comprises a plurality of memory units each made up of a plurality of blocks of addressable memory locations. A designated one of the blocks is required to be accessed in combination with the remainder of the blocks. Logic circuits are responsive to first and second groups of address bits to generate signals which enable a selected one of the memory units and access a selected one of the blocks on the selected unit. The designated block is accessed directly by one of the aforesaid groups of address bits.

Abstract: A personal computer transfers the contents of the computer's slow 16 bit read only memory (ROM) into the computer's fast 32 bit random access memory (RAM), remaps the RAM space to include the ROM space and disables the ROM. Portions of the RAM are tested before the contents are transferred. After the transfer the computer operates out of the RAM. Additionally, the RAM address space containing the ROM contents can selectively be made write protected so that the data cannot be changed.

Abstract: An integer processing unit for a reduced instruction set computer having a plurality of registers arranged in groups referred to as register windows, each window register group including a number of input registers, a similar number of output registers, and a number of local registers, the register window groups being physically arranged so the input registers of each group are the same physical register as the output registers of the next adjacent register window group thereby forming one large interconnected ring of register window groups, an arrangement for designating the register window group presently active, and an arrangement for designating register window groups which are not available for use.