Patents Examined by Laura M Menz
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Patent number: 12218230Abstract: A p-GaN high-electron-mobility transistor, includes a substrate, a channel layer stacked on the substrate, a supply layer stacked on the channel layer, a first doped layer stacked on the supply layer, a second doped layer stacked on the first doped layer, and a third doped layer stacked on the second doped layer. A doping concentration of the first doped layer and the doping concentration of the third doped layer are lower than a doping concentration of the second doped layer. A gate is located on the third doped layer, and a source and a drain are electrically connected to the channel layer and the supply layer, respectively.Type: GrantFiled: July 19, 2022Date of Patent: February 4, 2025Assignee: NATIONAL SUN YAT-SEN UNIVERSITYInventors: Ting-Chang Chang, Mao-Chou Tai, Yu-Xuan Wang, Wei-Chen Huang, Ting-Tzu Kuo, Kai-Chun Chang, Shih-Kai Lin
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Patent number: 12211741Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.Type: GrantFiled: November 10, 2023Date of Patent: January 28, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hui Huang, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Sheng-Chan Li
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Patent number: 12211837Abstract: Provided is a semiconductor device which may include: a channel structure; a gate structure on the channel structure; and a gate contact structure on the gate structure, the gate contact structure configured to receive a gate input signal, wherein the gate contact structure is a portion of the gate structure itself, and no connection surface, interface or boundary is formed between the gate contact structure and the gate structure.Type: GrantFiled: March 25, 2024Date of Patent: January 28, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myunghoon Jung, Jaehong Lee, Seungchan Yun, Kang-ill Seo
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Patent number: 12209014Abstract: The present disclosure provides a method for preparing a MEMS micro mirror with electrodes on both sides. The method includes: providing a first base, forming an electrode lead groove in the first base; forming an insulating groove, a plurality of lower comb plates and a moving space groove in a first device layer to obtain a bonded structure layer; providing a second base bonded with the bonded structure layer to obtain a bonded piece; forming a frame, upper comb plates, movable micro light reflector, and elastic beams in a second device layer, with the movable micro light reflector located inside the frame, and the elastic beam connected with the frame and/or the movable micro light reflector; forming a metal reflecting layer, a first upper comb plate electrode, a first lower comb plate electrode, a second upper comb plate electrode and a second lower comb plate electrode.Type: GrantFiled: December 22, 2021Date of Patent: January 28, 2025Assignee: Anhui China Science MW Electronic Technology Co., Ltd.Inventors: Wei Li, Jing Xu
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Patent number: 12205997Abstract: An integrated circuit includes a first chip bonded to a second chip. The first chip includes gate all around transistors on a substrate. The first chip includes backside conductive vias extending through the substrate to the gate all around transistors. The second chip includes electronic circuitry electrically connected to the transistors by the backside conductive vias.Type: GrantFiled: October 14, 2021Date of Patent: January 21, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Chung-Liang Cheng
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Patent number: 12206046Abstract: Various embodiments of SST dies and solid state lighting (“SSL”) devices with SST dies, assemblies, and methods of manufacturing are described herein. In one embodiment, a SST die includes a substrate material, a first semiconductor material and a second semiconductor material on the substrate material, an active region between the first semiconductor material and the second semiconductor material, and a support structure defined by the substrate material. In some embodiments, the support structure has an opening that is vertically aligned with the active region.Type: GrantFiled: February 12, 2024Date of Patent: January 21, 2025Assignee: Micron Technology, Inc.Inventors: Vladimir Odnoblyudov, Martin F. Schubert
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Patent number: 12205645Abstract: A process for fabricating a three-dimensional NOR memory string of storage transistors implements a channel-last fabrication process with channel replacement using silicon germanium (SiGe). In particular, the process uses silicon germanium as a sacrificial layer, to be replaced with the channel material after the charge-storage layer of the storage transistors is formed. In this manner, the channel region is prevented from experiencing excessive high-temperature processing steps, such as during the annealing of the charge-storage layer.Type: GrantFiled: April 18, 2022Date of Patent: January 21, 2025Assignee: SUNRISE MEMORY CORPORATIONInventors: Shohei Kamisaka, Vinod Purayath
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Patent number: 12201040Abstract: An electronic device includes a substrate, a source electrode layer and a drain electrode layer that are disposed to be spaced apart from each other over the substrate, a channel layer that is capable of receiving hydrogen, disposed between the source electrode layer and the drain electrode layer over the substrate, a proton conductive layer disposed on the channel layer, a hydrogen source layer disposed on the proton conductive layer, and a gate electrode layer disposed on the hydrogen source layer.Type: GrantFiled: August 11, 2021Date of Patent: January 14, 2025Assignee: SK hynix Inc.Inventors: Won Tae Koo, Jae Hyun Han
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Patent number: 12199015Abstract: A semiconductor device according to some example embodiments includes a substrate, an insulating structure covering the substrate, a transistor between the substrate and the insulating structure, a via insulating layer extending through the insulating structure and the substrate, a plurality of via structures extending through the via insulating layer, a plurality of conductive structures respectively connected to the plurality of via structures, and a plurality of bumps respectively connected to the conductive structures.Type: GrantFiled: January 13, 2022Date of Patent: January 14, 2025Assignee: Samsung Electronics Co., Ltd.Inventors: Yeonjin Lee, Jongmin Lee, Jeonil Lee
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Patent number: 12198999Abstract: An electronic package includes a carrier, a protection layer and an electronic component. The carrier includes a dielectric layer and a pad in contact with the dielectric layer. The protection layer at least partially covers the pad. The electronic component is located over the protection layer and electrically connected to the pad. At least one portion of the protection layer under the electronic component is substantially conformal with a profile of the pad or with a profile of the dielectric layer.Type: GrantFiled: September 16, 2021Date of Patent: January 14, 2025Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: You-Lung Yen, Bernd Karl Appelt
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Patent number: 12199096Abstract: A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.Type: GrantFiled: February 8, 2024Date of Patent: January 14, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung Seok Ha, Hyun Seung Song, Hyo Jin Kim, Kyoung Mi Park, Guk Il An
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Patent number: 12199002Abstract: A semiconductor package includes a first semiconductor chip including first through electrodes and having a first hot zone in which the first through electrodes are disposed; a heat redistribution chip disposed on the first semiconductor chip, having a cool zone overlapping the first hot zone in a stacking direction with respect to the first semiconductor chip, and including first heat redistribution through electrodes disposed outside of an outer boundary of the cool zone and electrically connected to the first through electrodes, respectively; a second semiconductor chip disposed on the heat redistribution chip, having a second hot zone overlapping the cool zone in the stacking direction, and including second through electrodes disposed in the second hot zone and electrically connected to the first heat redistribution through electrodes, respectively; and a first thermal barrier layer disposed between the first hot zone and the cool zone, wherein the first through electrodes are electrically connected to thType: GrantFiled: May 4, 2022Date of Patent: January 14, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Taehwan Kim, Kyungsuk Oh, Jaechoon Kim
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Patent number: 12191055Abstract: A method for fabricating a micro resistance layer and a method for fabricating a micro resistor are provided. The method for fabricating a micro resistance layer includes: providing a substrate; forming a first resistance layer on the substrate by using a screen printing process or a sputtering process; dividing the first resistance layer into second resistance layers, wherein each one of the product regions includes a second resistance layer, and an area of each one of the product regions is smaller than 0.4*0.2 mm2; and trimming the second resistance layer of each one of the product regions according to a predetermined resistance value to enable the pattern of each one of the second resistance layers to correspond to the predetermined resistance value. The method for fabricating a micro resistor uses the method for fabricating a micro resistance layer for fabrication of the micro resistor.Type: GrantFiled: March 15, 2022Date of Patent: January 7, 2025Assignee: YAGEO CORPORATIONInventors: Shen-Li Hsiao, Chih-Wei Chi
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Patent number: 12191345Abstract: A semiconductor device includes a substrate; a first semiconductor region formed over the substrate; a second semiconductor region formed over the substrate, and electrically connected to the first semiconductor region; a third semiconductor region formed over the substrate, and positioned between the first semiconductor region and the second semiconductor region; a fourth semiconductor region formed over the first semiconductor region; a fifth semiconductor region formed over the second semiconductor region, and electrically connected to the fourth semiconductor region; a sixth semiconductor region formed over the third semiconductor region, and positioned between the fourth semiconductor region and the fifth semiconductor region; and wires formed between the first semiconductor region and the second semiconductor region, and between the fourth semiconductor region and the fifth semiconductor region, to cover the third semiconductor region and the sixth semiconductor region, the wires including conductors.Type: GrantFiled: March 7, 2024Date of Patent: January 7, 2025Assignee: SOCIONEXT INC.Inventors: Isaya Sobue, Hideyuki Komuro
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Patent number: 12191253Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a fuse element, and a fuse medium. The fuse element is disposed within the substrate. The fuse medium surrounds a lateral surface of the fuse element.Type: GrantFiled: June 14, 2022Date of Patent: January 7, 2025Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Hsih-Yang Chiu
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Patent number: 12191197Abstract: A manufacturing method of a package structure of an electronic device, including the following steps, is provided. A first seed layer is formed on a carrier plate. A first metal layer is formed on the first seed layer. A first insulating layer is formed on the first metal layer, wherein the first insulating layer exposes a portion of the first metal layer. A first plasma treatment is performed on the first insulating layer and the exposed portion of the first metal layer. After performing the first plasma treatment, the carrier plate formed with the first seed layer, the first metal layer, and the first insulating layer is placed in a microenvironment controlling box. After taking the carrier plate out of the microenvironment controlling box, a second seed layer is formed on the first insulating layer and the exposed portion of the first metal layer.Type: GrantFiled: May 18, 2022Date of Patent: January 7, 2025Assignee: Innolux CorporationInventors: Ching-Wei Chen, Yu-Jen Chang, Tzu-Yen Chiu, Hung-I Tseng, Chuan-Ming Yeh, Heng-Shen Yeh
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Patent number: 12191303Abstract: A semiconductor device structure including a doped region under an isolation feature is provided. The semiconductor device structure includes a first substrate, a first well region, a first gate structure, a second gate structure, a first doped region, and a first conductive feature. The substrate has a first surface and a second surface opposite to the first surface. The first well region is in the first substrate. The first well region has a first conductive type. The first gate structure is disposed on the second surface. The second gate structure is disposed on the second surface. The first doped region includes a second conductive type different from the first conductive type. The first doped region is disposed between the first gate structure and the second gate structure. The first conductive feature extends between the first surface of the first substrate and the first doped region.Type: GrantFiled: April 15, 2024Date of Patent: January 7, 2025Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Hsih-Yang Chiu
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Patent number: 12185546Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure. The microelectronic device structure comprises a stack structure comprising insulative structures and additional insulative structures vertically alternating with the insulative structures, a dielectric structure vertically extending partially through the stack structure, and a dielectric material vertically overlying and horizontally extending across the stack structure and the dielectric structure. Portions of at least the dielectric material and the dielectric structure are removed to form a trench vertically overlying and at least partially horizontally overlapping a remaining portion of the dielectric structure. The trench is substantially filled with additional dielectric material. Microelectronic devices, memory devices, and electronic systems are also described.Type: GrantFiled: June 28, 2023Date of Patent: December 31, 2024Assignee: Loestar Licensing Group LLCInventors: Shuangqiang Luo, Indra V. Chary, Justin B. Dorhout
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Patent number: 12183586Abstract: An embodiment of the application provides a method for forming a semiconductor structure. The semiconductor structure includes a first region and a second region. The method includes the following steps: providing a base, an insulating layer, and a mask layer that are stacked in sequence, where the first region has at least one trench penetrating the mask layer and the insulating layer, and the mask layer has an upper surface in the second region higher than that in the first region; forming a first protection layer, where an upper surface and a sidewall of the mask layer in the first region are covered with the first protection layer; after the first protection layer is formed, removing the mask layer in the second region; subsequent to removal of the mask layer in the second region, removing the first protection layer; and removing the mask layer in the first region.Type: GrantFiled: October 19, 2021Date of Patent: December 31, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Jun Xia, Kangshu Zhan, Sen Li, Penghui Xu, Qiang Wan, Tao Liu
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Patent number: 12176291Abstract: An electronic package is provided in which a chip packaging module, an electronic element having a plurality of contacts, and an electronic connector are disposed on a routing structure of a carrier component, so as to communicatively connect with the chip packaging module via the electronic element and the electronic connector, thereby increasing a signal transmission speed.Type: GrantFiled: May 10, 2022Date of Patent: December 24, 2024Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chao-Chiang Pu, Chi-Ching Ho, Yi-Min Fu, Yu-Po Wang, Shuai-Lin Liu