Patents Examined by Laura M Menz
  • Patent number: 11121134
    Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: September 14, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang Ho Lee, Eun A Kim, Ki Seok Lee, Jay-Bok Choi, Keun Nam Kim, Yong Seok Ahn, Jin-Hwan Chun, Sang Yeon Han, Sung Hee Han, Seung Uk Han, Yoo Sang Hwang
  • Patent number: 11121135
    Abstract: A structure of memory cell includes a substrate. The substrate includes a first active region, a second active region and a first shallow trench isolation (STI) structure between the first active region and the second active region, wherein the first active region is lower than the second active region. A first contact structure is disposed on the first active region. A first stack structure is on the first contact structure. A second contact structure is on the substrate with a bottom portion in the substrate at an interface between the second active region and the first STI structure. A dielectric spacer is at least on a sidewall of the first contact structure. An insulating layer is disposed on the dielectric spacer and between the second contact structure and the first contact structure with the first stack structure, wherein a dielectric constant of the dielectric spacer is lower than a dielectric constant of the insulating layer.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: September 14, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Noriaki Ikeda
  • Patent number: 11111132
    Abstract: An micro electro mechanical sensor comprising: a substrate; and a sensor element movably mounted to a first side of said substrate; wherein a second side of said substrate has a pattern formed in relief thereon. The pattern formed in relief on the second side of the substrate provides a reduced surface area for contact with the die bond layer. The reduced surface area reduces the amount of stress that is transmitted from the die bond layer to the substrate (and hence reduces the amount of transmitted stress reaching the MEMS sensor element). Because the substrate relief pattern provides a certain amount of stress decoupling, the die bond layer does not need to decouple the stress to the same extent as in previous designs. Therefore a thinner die bond layer can be used, which in turn allows the whole package to be slightly thinner.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: September 7, 2021
    Assignee: ATLANTIC INERTIAL SYSTEMS LIMITED
    Inventors: Michael Durston, Kevin Townsend
  • Patent number: 11114408
    Abstract: Systems and methods for providing 3D wafer assembly with known-good-dies are provided. An example method compiles an index of dies on a semiconductor wafer and removes the defective dies to provide a wafer with dies that are all operational. Defective dies on multiple wafers may be removed in parallel, and resulting wafers with all good dies stacked in 3D wafer assembly. In an implementation, the spaces left by removed defective dies may be filled at least in part with operational dies or with a fill material. Defective dies may be replaced either before or after wafer-to-wafer assembly to eliminate production of defective stacked devices, or the spaces may be left empty. A bottom device wafer may also have its defective dies removed or replaced, resulting in wafer-to-wafer assembly that provides 3D stacks with no defective dies.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: September 7, 2021
    Assignee: Invensas Corporation
    Inventors: Hong Shen, Liang Wang, Guilian Gao
  • Patent number: 11107907
    Abstract: A method for manufacturing a semiconductor device includes forming a dummy gate structure on a semiconductor fin; forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure; removing the dummy gate structure from the semiconductor fin; forming a gate structure on the semiconductor fin and between the gate spacers, wherein the gate structure comprises a gate dielectric layer and a work function metal over the gate dielectric layer; performing a first plasma etching process by using a first reactant to etch back the gate structure performing a second plasma etching process by using a second reactant on the etched-back gate structure, wherein the first plasma etching process has a first removal rate of the gate dielectric layer, the second plasma etching process has a second removal rate of the gate dielectric layer, and the second removal rate is greater than the first removal rate.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Hao Chang, Li-Te Lin
  • Patent number: 11107874
    Abstract: A display device includes: a flexible substrate; a plurality of conductive lines on the flexible substrate; a thin film transistor connected to the plurality of conductive lines; and an organic light emitting element connected to the thin film transistor. As a curvature of an area of the flexible substrate increases, a width or a thickness of each of the conductive lines increases.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: August 31, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Minsung Kim, Hyunwoo Koo, Tae Woong Kim, Jin Hwan Choi, Hayk Kachatryan
  • Patent number: 11107951
    Abstract: Heterostructures containing one or more sheets of positive charge, or alternately stacked AlGaN barriers and AlGaN wells with specified thickness are provided. Also provided are multiple quantum well structures and p-type contacts. The heterostructures, the multiple quantum well structures and the p-type contacts can be used in light emitting devices and photodetectors.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: August 31, 2021
    Assignee: BOLB INC.
    Inventors: Jianping Zhang, Ying Gao, Ling Zhou
  • Patent number: 11107932
    Abstract: There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: August 31, 2021
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventor: Huilong Zhu
  • Patent number: 11101541
    Abstract: A semiconductor assembly includes a first wiring structure, a first semiconductor die and a first electronic element. The first wiring structure has a first surface. The first semiconductor die is disposed on the first surface of the first wiring structure. The first electronic element is electrically connected to the first wiring structure. The first electronic element includes a first metal layer, a second metal layer and a dielectric material interposed between the first metal layer and the second metal layer. The first metal layer and the second metal layer are substantially perpendicular to the first surface of the first wiring structure.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: August 24, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 11101254
    Abstract: A system in package and method for making a system in package. A plurality of passive devices are coupled to an interposer. A molding compound envelopes the plurality of passive devices and defines a platform having a substantially planar surface. The interposer is coupled to a substrate. A plurality of integrated circuit dies are coupled in a stack to the planar surface.
    Type: Grant
    Filed: December 25, 2015
    Date of Patent: August 24, 2021
    Assignee: Intel Corporation
    Inventors: Zhicheng Ding, Bin Liu
  • Patent number: 11094801
    Abstract: According to an embodiment of the present invention, a semiconductor structure includes a semiconductor substrate and a plurality of fins located on the semiconductor substrate. The plurality of fins each independently includes a bottom fin portion, a top fin portion layer, and an isolated oxide layer located in between the bottom fin portion and the top fin portion layer in the y-direction parallel to the height of the plurality of fins. The isolated oxide layer includes a mixed oxide region located in between oxidized regions in an x-direction perpendicular to the height of the plurality of fins.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: August 17, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Paul C. Jamison, Choonghyun Lee
  • Patent number: 11094732
    Abstract: An image sensor having pixels that include two patterned semiconductor layers. The top patterned semiconductor layer contains the photoelectric elements of pixels having substantially 100% fill-factor. The bottom patterned semiconductor layer contains transistors for detecting, resetting, amplifying and transmitting signals charges received from the photoelectric elements. The top and bottom patterned semiconductor layers may be separated from each other by an interlayer insulating layer that may include metal interconnections for conducting signals between devices formed in the patterned semiconductor layers and from external devices.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: August 17, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jung-Chak Ahn
  • Patent number: 11087973
    Abstract: Embodiments of the invention address several issues and problems associated with etching of dielectric materials for BEOL applications. According to one embodiment, the method includes providing a patterned substrate containing a dielectric material, exposing the substrate to a gas phase plasma to functionalize a surface of the dielectric material, exposing the substrate to a silanizing reagent that reacts with the functionalized surface of the dielectric material to form a dielectric film, and sequentially repeating the exposing steps at least once to increase a thickness of the dielectric film. According to one embodiment, the dielectric material may be a porous low-k material, and the dielectric film seals the pores on a surface of the porous low-k material.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: August 10, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Yannick Feurprier, Doni Parnell
  • Patent number: 11088055
    Abstract: A package includes a leadframe having first surface and a second surface opposing the first surface, the leadframe forming a plurality of leads, a first semiconductor die mounted on the first surface of the leadframe and electrically connected to at least one of the plurality of leads, a second semiconductor die mounted on the second surface of the leadframe, wire bonds electrically connecting the second semiconductor die to the leadframe, and mold compound at least partially covering the first semiconductor die, the second semiconductor die and the wire bonds.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: August 10, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Makoto Shibuya, Noboru Nakanishi
  • Patent number: 11088048
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor includes a substrate, a block bonded on the substrate, a first die bonded on the block, a second die disposed over the first die, and a heat spreader covering the block and having a surface facing toward and proximal to the block. A thermal conductivity of the heat spreader is higher than a thermal conductivity of the block.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Hsi Wu, Wensen Hung, Tsung-Shu Lin, Shih-Chang Ku, Tsung-Yu Chen, Hung-Chi Li
  • Patent number: 11081573
    Abstract: A semiconductor element includes a semiconductor substrate; a collector layer on the semiconductor substrate; a base layer on the collector layer; an emitter layer on the base layer; emitter wiring electrically coupled to the emitter layer; a top metal layer on the emitter wiring; a first protective film covering the emitter wiring and the top metal layer, the first protective film having a first opening that overlaps at least the collector layer; and a bump including an under-bump metal layer electrically coupled to the emitter wiring via the first opening, the under-bump metal layer being larger than the first opening in plan-view area. The first protective film has an inner edge around the first opening, and the inner edge is on the top metal layer.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: August 3, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Atsushi Kurokawa, Kazuya Kobayashi
  • Patent number: 11081372
    Abstract: A package system includes a first interposer including a first substrate having first and second primary surfaces on opposite sides of the first substrate. The package system includes a first interconnect structure over the first surface, the first interconnect structure having a first metallic line pitch LP1. The package system includes a plurality of first through silicon via (TSV) structures in the first substrate. The package system includes a molding compound material partially enveloping the first substrate. The package system includes a plurality of through vias in the molding compound material, wherein each through via of the plurality of through vias is offset from the first substrate. The package system includes a second interconnect structure on a second surface of the first substrate. The second interconnect structure has a second metallic line pitch LP2, and LP2>LP1. The package system includes a first integrated circuit over the first interposer.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng Wu, Shang-Yun Hou, Shin-Puu Jeng, Chen-Hua Yu
  • Patent number: 11075306
    Abstract: Implementations of semiconductor packages may include: a wafer having a first side and a second side, a solder pad coupled to the first side of the wafer, a through silicon via (TSV) extending from the second side of the wafer to the solder pad a metal layer around the walls of the TSV, and a low melting temperature solder in the TSV. The low melting temperature solder may also be coupled to the metal layer. The low melting temperature solder may couple to the solder pad through an opening in a base layer metal of the solder pad.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: July 27, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Bingzhi Su
  • Patent number: 11075313
    Abstract: A growth structure having a lattice transition (or graded buffer) or an engineered growth structure with a desired lattice constant, different from a lattice constant of conventional substrates like GaAs, Si, Ge, InP, under a release layer or an etch stop layer is used as a seed crystal for growing optoelectronic devices. The optoelectronic device can be a photovoltaic device having one or more subcells (e.g., lattice-matched or lattice-mismatched subcells). The release layer can be removed using different processes to separate the optoelectronic device from the growth structure, which may be reused, or from the engineered growth structure. When using the etch stop layer, the growth structure or the engineered growth structure may be grinded or etched away. The engineered growth structure may be made from a layer transfer process between two wafers or from a ternary and/or a quaternary material. Methods for making the optoelectronic device are also described.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: July 27, 2021
    Assignee: UTICA LEASECO, LLC
    Inventors: Nikhil Jain, Andrew J. Ritenour, Ileana Rau, Claudio Canizares, Lori D. Washington, Gang He, Brendan M. Kayes
  • Patent number: 11075197
    Abstract: A resistor including a device isolation layer is described that includes a first active region and a second active region, a buried insulating layer, and an N well region. The N well region surrounds the first active region, the second active region, the device isolation layer and the buried insulating layer. A first doped region and a second doped region are disposed on the first active region and the second active region. The first doped region and the second doped region are in contact with the N well region and include n type impurities.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: July 27, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woocheol Shin, Myunggil Kang, Minyi Kim, Sanghoon Lee