Abstract: A power semiconductor module arrangement includes two or more individual semiconductor devices arranged on a base layer. Each semiconductor device includes a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame. A frame is arranged on the base layer such that the frame surrounds the two or more individual semiconductor devices. A casting compound at least partly fills a capacity formed by the base layer and the frame, such that the casting compound at least partly encloses the two or more individual semiconductor devices.

Abstract: A micromechanical component for a capacitive pressure sensor device, including a diaphragm that is stretched with the aid of a frame structure in such a way that a cantilevered area of the diaphragm spans a framed partial surface, and including a reinforcement structure that is formed at the cantilevered area. A first spatial direction oriented in parallel to the framed partial surface is definable in which the cantilevered area has a minimal extension, and a second spatial direction oriented in parallel to the framed partial surface and oriented perpendicularly with respect to the first spatial direction is definable in which the cantilevered area has a greater extension. The reinforcement structure is present at a first distance from the frame structure in the first spatial direction, and at a second distance in the second spatial direction, the second distance being greater than the first distance.

Abstract: A power semiconductor module includes: an electrically insulative frame having opposite first and second mounting sides, and a border that defines a periphery of the electrically insulative frame; a first substrate seated in the electrically insulative frame; a plurality of power semiconductor dies attached to the first substrate; a plurality of signal pins attached to the first substrate and electrically connected to the power semiconductor dies; a plurality of busbars attached to the first substrate and extending through the border of the electrically insulative frame; a plurality of fixing positions at the first mounting side of the electrically insulative frame; and a plurality of electrically insulative protrusions jutting out from the second mounting side of the electrically insulative frame, wherein the protrusions are vertically aligned with the fixing positions.

Abstract: A semiconductor device includes: a first conductive plate and a second conductive plate disposed adjacent to the first conductive plate; a first insulating plate disposed over the first conductive plate and the second conductive plate; a third conductive plate disposed over the first insulating plate; a second insulating plate disposed over the third conductive plate; a fourth conductive plate disposed over the second insulating plate; a first conductive via penetrating the fourth conductive plate, the second insulating plate, the first insulating plate, and the first conductive plate, wherein the first conductive via is electrically coupled to the fourth conductive plate and the first conductive plate; and a second conductive via penetrating the second insulating plate, the third conductive plate, the first insulating plate, and the second conductive plate, wherein the second conductive via is electrically coupled to the third conductive plate and the second conductive plate.

Abstract: A stacked via structure including a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer and a second conductive via is provided. The first dielectric layer includes a first via opening. The first conductive via is in the first via opening. A first level height offset is between a top surface of the first conductive via and a top surface of the first dielectric layer. The first redistribution wiring covers the top surface of the first conductive via and the top surface of the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer and the first redistribution wiring. The second dielectric layer includes a second via opening. The second conductive via is in the second via opening. The second conductive via is electrically connected to the first redistribution wiring through the second via opening of the second dielectric layer.

Abstract: The disclosure discloses a layout structure of an eFuse unit, comprising pad, link, and shield, wherein: a pad is respectively disposed on both ends of the link in a length direction; the shield and the link are at the same metal layer; the shield comprises a plurality of independent metal wires; the plurality of independent metal wires are arranged on both sides of the link; the length of each independent metal wire is greater than the width thereof; and a length direction of each independent metal wire is perpendicular to the length direction of the link. The disclosure not only forms a barrier protection layer for preventing burst metal spraying from affecting other circuits, but also can prevent spayed metal from reflecting back and connecting to a broken link, so as to improve the programming reliability of the eFuse unit.

Abstract: An integrated semiconductor device includes a substrate, semiconductor circuit layers, a first insulating layer, a second insulating layer, and an interconnection layer. The semiconductor circuit layers are disposed above the substrate. The semiconductor circuit layers have device portions and isolating portions, and the isolating portions are located among the device portions. The first insulating layer is disposed on the semiconductor circuit layers, and the second insulating layer is disposed on the first insulating layer, and the interconnection layer is disposed on the semiconductor circuit layers. The interconnection layer penetrates the first and second insulating layers to electrically connect the device portions of the semiconductor circuit layers. The second insulating layer or the first and second insulating layers collectively form one or more isolating structures above the isolating portion of the semiconductor circuit layers.

Abstract: An integrated semiconductor device includes a substrate, semiconductor circuit layers, an insulating material, and an interconnection layer. The semiconductor circuit layers are disposed above the substrate. The semiconductor circuit layers have device portions and isolating portions, and the isolating portions are located among the device portions. The insulating material is disposed on the semiconductor circuit layers, and the interconnection layer is embedded in the insulating material and electrically connected to the semiconductor circuit layers. The isolating portions provide electrical isolation between adjacent device portions. The interconnection layer has circuits embedded in the insulating material on the device portions. The insulating material has isolating structures raised from top surfaces of the circuits on the device portion, and some of the semiconductor circuit layers form at least one heterojunction.

Abstract: A Fan-Out package having a main die and a dummy die side-by-side is provided. A molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die.

Abstract: A semiconductor device with a sidewall interconnection structure and a method for manufacturing the same, and an electronic apparatus including the semiconductor device are provided. According to embodiments, the semiconductor device includes: a vertical stack including a plurality of element layers, wherein each element layer of the plurality of element layers includes a plurality of semiconductor elements and a metallization layer for the plurality of semiconductor elements; and an interconnection structure laterally adjoined the vertical stack. The interconnection structure includes: an electrical isolation layer; and a conductive structure in the electrical isolation layer, wherein at least a part of a conductive structure in the metallization layer of the each element layer is in contact with and electrically connected to the conductive structure at a corresponding height in the interconnection structure in a lateral direction.

Abstract: Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a filament and one or more lateral regions including a doping material that are between a top region and a bottom region of the switching layer. The RRAM further includes a top electrode disposed above the switching layer.

Abstract: A semiconductor device including a semiconductor structure including a first semiconductor layer, a second semiconductor layer, and an active layer; a first electrode provided on a first surface of the first semiconductor layer; a second electrode provided on a first surface of the second semiconductor layer, the active layer being provided between the first surface of the first semiconductor layer and a second surface of the second semiconductor layer that is opposite to the first surface of the second semiconductor layer; a first insulation layer provided on the first surface of the first semiconductor layer, the first surface of the second semiconductor layer, and a side surface of the active layer; a first cover electrode provided on the first electrode; a second cover electrode provided on the second electrode, a second insulation layer provided on the first cover electrode, the second cover electrode, and the first insulation layer, wherein: the second insulation layer includes a first opening over the

Abstract: A method provides a circuit carrier arrangement that includes: a cooling plate (1) which has spacer and fastening elements (3) for connection to a printed circuit board (2) in a spaced-apart manner; a printed circuit board (2) which has bores (4) for receiving spring element sleeves (9); at least one power semiconductor component (10) which is connected by a soldered connection to the printed circuit board (2) and fastening elements (3) in the state in which it is fitted with the cooling plate (1) by means of plug-in connections (11) of spring-action configuration; and at least one spring element (5) having at least two spring element sleeves (9) between which a web (6) that is connected to the spring element sleeves (9) extends, and supporting elements (7) arranged on either side of said web and at least one spring plate (8) being arranged on said web.

Abstract: A semiconductor device includes a substrate; a first semiconductor region formed over the substrate; a second semiconductor region formed over the substrate, and electrically connected to the first semiconductor region; a third semiconductor region formed over the substrate, and positioned between the first semiconductor region and the second semiconductor region; a fourth semiconductor region formed over the first semiconductor region; a fifth semiconductor region formed over the second semiconductor region, and electrically connected to the fourth semiconductor region; a sixth semiconductor region formed over the third semiconductor region, and positioned between the fourth semiconductor region and the fifth semiconductor region; and wires formed between the first semiconductor region and the second semiconductor region, and between the fourth semiconductor region and the fifth semiconductor region, to cover the third semiconductor region and the sixth semiconductor region, the wires including conductors.

Abstract: A resistor including a device isolation layer is described that includes a first active region and a second active region, a buried insulating layer, and an N well region. The N well region surrounds the first active region, the second active region, the device isolation layer and the buried insulating layer. A first doped region and a second doped region are disposed on the first active region and the second active region. The first doped region and the second doped region are in contact with the N well region and include n type impurities.

Abstract: A bonded structure is disclosed. The bonded structure includes a first element and a second element that is bonded to the first element along a bonding interface. The bonding interface has an elongate conductive interface feature and a nonconductive interface feature. The bonded structure also includes an integrated device that is coupled to or formed with the first element or the second element. The elongate conductive interface feature has a recess through a portion of a thickness of the elongate conductive interface feature. A portion of the nonconductive interface feature is disposed in the recess.

Abstract: An electronic device is provided and includes a first electrode, a second electrode and a photoelectric conversion layer sandwiched between the first electrode and the second electrode, the first electrode including an amorphous oxide including a quaternary compound including one or more of indium, gallium and aluminum and further including zinc and oxygen, the first electrode having a laminated structure including a first B layer and a first A layer from a photoelectric conversion layer side, and a work function value of the first A layer of the first electrode being lower than a work function of the first B layer of the first electrode.

Abstract: The present disclosure provides a semiconductor device, a semiconductor assembly and method of manufacturing the semiconductor assembly. The semiconductor device includes a substrate, a conductive feature in the substrate, an isolation liner between the substrate and the conductive feature, and a main component in the substrate. The conductive feature includes first to third blocks. The first block has a uniform first critical dimension, wherein the main component is disposed around the first block. The second block has a uniform second critical dimension greater than the first critical dimension. The third block is interposed between the first block and the second block and has varying third critical dimensions.

Abstract: Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).

Abstract: Systems for physical unclonable function (“PUF”) generation, PUF devices, and methods for manufacturing PUF devices. In one implementation, the system includes a plurality of PUF devices and an electronic controller. Each of the plurality of PUF devices include a first electrochemically-inactive electrode, a second electrochemically-inactive electrode, and a layer of silicon suboxide. The layer of silicon suboxide is positioned directly between the first electrochemically-inactive electrode and the second electrochemically-inactive electrode. The electronic controller is communicably coupled to the plurality of PUF devices. The electronic controller is configured to read binary values associated with the plurality of PUF devices.