Patents Examined by Laura M Menz
  • Patent number: 11462453
    Abstract: The present application discloses a semiconductor device with protection layers for reducing the metal to silicon leakage and a method for fabricating the semiconductor device. The semiconductor device includes a first die, a first conductive feature positioned in the first die, a second die positioned on the first die, a first mask layer positioned on the second die, a conductive filler layer positioned along the first mask layer and the second die, extending to the first die, and contacting the first conductive feature, isolation layers positioned between the conductive filler layer and the first die and between the conductive filler layer and the second die, and protection layers positioned between the conductive filler layer and the first mask layer and covering upper portions of the isolation layers.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: October 4, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Tse-Yao Huang, Shing-Yih Shih
  • Patent number: 11456269
    Abstract: A method of fabricating a connection structure is disclosed. The method includes providing a substrate that has a top surface and includes a set of pads for soldering, each of which has a pad surface exposed from the top surface of the substrate. The method also includes applying a surface treatment to a part of the top surface of the substrate close to the pads and the pad surface of each pad so as to make at least the part of the top surface and the pad surfaces of the pads rougher. The surface treatment includes sandblasting.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: September 27, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Risa Miyazawa, Takahito Watanabe, Hiroyuki Mori, Keishi Okamoto
  • Patent number: 11456237
    Abstract: A semiconductor storage device according to one embodiment includes a substrate; a memory cell area having a stacked body where plural electrically conductive layers and plural first insulating layers are stacked alternately one on another, and a pillar portion that penetrates through the stacked body and provides plural memory cells; a peripheral circuit portion that intervenes between the substrate and the memory cell area, and includes a peripheral circuit for plural memory cells; a first plate-like portion that has a frame-like plan view shape and surrounds the peripheral circuit portion, the first plate-like portion being electrically conductive and connected at a lower end thereof to the substrate; a sidewall layer including silicon nitride on a side surface of the first plate-like portion; and a second insulating layer including silicon nitride, the second insulating layer being connected to the sidewall layer and covering above the peripheral circuit portion.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: September 27, 2022
    Assignee: Kioxia Corporation
    Inventor: Masako Kinoshita
  • Patent number: 11437404
    Abstract: A FET IC structure made using a back-side access process that mitigates or eliminates thermal conductivity problems. In some embodiments, electrically-isolated thermal paths are formed adjacent the FET and configured to conduct heat laterally away from the FET to generally orthogonal thermal pathways, and thence to thermal pads externally accessible at the “top” of the completed IC. In some embodiments having a thermally-conductive handle wafer, electrically-isolated thermal paths are formed adjacent a FET and configured to conduct heat laterally away from the FET. Thermal vias are formed sufficiently so as to be in thermal contact with the handle wafer and with the conventional metallization layers of the device superstructure, at least one of which is in thermal contact with the lateral thermal paths. In some embodiments, the lateral thermal paths may use dummy gates configured to conduct heat laterally away from a FET to generally orthogonal thermal pathways.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: September 6, 2022
    Assignee: pSemi Corporation
    Inventors: Abhijeet Paul, Richard James Dowling, Hiroshi Yamada, Alain Duvallet, Ronald Eugene Reedy
  • Patent number: 11437311
    Abstract: A method for producing a power semiconductor module arrangement includes arranging two or more individual semiconductor devices on a base layer, each semiconductor device including a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame, arranging a frame on the base layer such that the frame surrounds the two or more individual semiconductor devices, and filling a first material into a capacity formed by the base layer and the frame, and hardening the first material to form a casting compound that at least partly fills the capacity, thereby at least partly encloses the two or more individual semiconductor devices.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: September 6, 2022
    Assignee: Infineon Technologies AG
    Inventors: Olaf Hohlfeld, Peter Kanschat
  • Patent number: 11437084
    Abstract: The present disclosure relates to a method of forming a memory structure. The method includes depositing a ferroelectric random access memory (FeRAM) stack over a substrate. The FeRAM stack has a ferroelectric layer and one or more conductive layers over the ferroelectric layer. The FeRAM stack is patterned to define an FeRAM device stack. A sidewall spacer is formed along a first side of the FeRAM device stack, and a select gate is formed along a side of the sidewall spacer that faces away from the FeRAM device stack. A source region is formed within the substrate and along a second side of the FeRAM device stack, and a drain region is formed within the substrate. The drain region is separated from the FeRAM device stack by the select gate.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yu Chen, Kuo-Chi Tu, Wen-Ting Chu, Yong-Shiuan Tsair
  • Patent number: 11437351
    Abstract: A semiconductor device includes: a wiring board including first to third bonding pads; a chip stack including semiconductor chips, each chip having first to third connection pads, the first connection pads being connected in series to each other and to the first bonding pad through first bonding wires to form a first transmission channel, the second connection pads being connected in series to each other and to the second bonding pad through second bonding wires to form a second transmission channel, and the third connection pads being connected in series to each other and to the third bonding pad through third bonding wires to form a third transmission channel; and at least one of a first and a second terminating resistor being provided above the chip stack, the first resistor being connected to the first and second channels, the second resistor being connected to the first and third channels.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: September 6, 2022
    Assignee: Kioxia Corporation
    Inventor: Yasuo Otsuka
  • Patent number: 11424182
    Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: August 23, 2022
    Inventors: Suhyun Bark, Kyeongbeom Park, Jongmin Baek, Jangho Lee, Wookyung You, Deokyoung Jung
  • Patent number: 11424231
    Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and containing respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die includes a peripheral circuitry.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: August 23, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Adarsh Rajashekhar, Raghuveer S. Makala, Fei Zhou
  • Patent number: 11424265
    Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate including a single crystalline substrate semiconductor material, and memory stack structures extending through the alternating stack and containing a respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die contains a peripheral circuitry.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: August 23, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Adarsh Rajashekhar, Raghuveer S. Makala, Fei Zhou, Rahul Sharangpani
  • Patent number: 11410933
    Abstract: A package structure, including a bridge, an interposer, a first redistribution structure layer, a second redistribution structure layer, and multiple chips, is provided. The bridge includes a silicon substrate, a redistribution layer, and multiple bridge pads. The interposer includes an intermediate layer, multiple conductive vias, multiple first pads, and multiple second pads. The bridge is embedded in the intermediate layer. The bridge pads are aligned with the upper surface. The first redistribution structure layer is disposed on the upper surface of the interposer and is electrically connected to the first pads and the bridge pads. The second redistribution structure layer is disposed on the lower surface of the interposer and is electrically connected to the second pads. The chips are disposed on the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The chips are electrically connected to each other through the bridge.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: August 9, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: John Hon-Shing Lau, Cheng-Ta Ko, Pu-Ju Lin, Tzyy-Jang Tseng, Ra-Min Tain, Kai-Ming Yang
  • Patent number: 11410924
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing steps, memory stack structures extending through the alternating stack, a first contact via structure which contacts a top surface of a respective upper electrically conductive layer in a first step, a first dielectric spacer which does not contact any of the electrically conductive layers other than the respective upper electrically conductive layer in the first step, a second contact via structure which contacts a top surface of a respective lower electrically conductive layer in the first step, and a second dielectric spacer which extends through the respective upper electrically conductive layer, and which contacts the respective lower electrically conductive layer.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: August 9, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Haruki Suwa, Keisuke Shigemura, Akihiro Shimada
  • Patent number: 11410926
    Abstract: In the present disclosure, a semiconductor structure includes an Mx-1 layer including a first dielectric layer and first metal features, wherein the first metal features include a first set of first metal features in a first region and a second set of first metal features in a second region, wherein the first set has a first pattern density and the second set has a second pattern density being greater than the first pattern density. The structure further includes a Vx layer disposed over the Mx-1 layer, the Vx layer including first vias contacting the first set of the first metal features. The structure further includes an Mx layer disposed over the Vx layer, the Mx layer including a fuse element, wherein the fuse element has a first thickness in the first region less than a second thickness in the second region.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Jiao Fu, Po-Hsiang Huang, Derek Hsu, Hsiu-Wen Hsueh, Meng-Sheng Chang
  • Patent number: 11404390
    Abstract: Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: August 2, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Chao Wen Wang
  • Patent number: 11404532
    Abstract: An integrated circuit having a fingered capacitor with multiple metal fingers formed in inverted-trapezoid-shaped trenches in a multi-layer structure having a polish stop layer over an ultra-low-K dielectric layer over a low-K dielectric layer over a dielectric cap layer. The ultra-low-K dielectric layer reduces capacitance variations between the fingers, while the polish stop layer prevents metal height variations that would otherwise result from performing CMP directly on the ultra-low-K dielectric layer. The layered structure may include another low-K dielectric layer over the polish stop layer that provides a soft landing for the CMP. The polish stop layer may be removed after the CMP polishing and another ultra-low-K dielectric layer may be formed to encapsulate the tops of the metal fingers in the ultra-low-K dielectric material.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: August 2, 2022
    Assignee: NXP B.V.
    Inventors: Chunshan Yin, Cheong Min Hong, Yu Chen
  • Patent number: 11398451
    Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and containing respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die includes a peripheral circuitry. Substrates employed to provide the memory die and the support die can be reused by replacing one of the substrates with an alternative low-cost substrate that provides structural support to the bonded assembly.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: July 26, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ashish Baraskar, Raghuveer S. Makala, Peter Rabkin
  • Patent number: 11393783
    Abstract: A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Hui Cheng, Po-Hao Tsai, Jing-Cheng Lin
  • Patent number: 11393741
    Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Wai Ling Lee, Tat Hin Tan
  • Patent number: 11384449
    Abstract: In various embodiments, growth of large, high-quality single crystals of aluminum nitride is enabled via a two-stage process utilizing two different crystalline seeds.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: July 12, 2022
    Assignee: CRYSTAL IS, INC.
    Inventors: Leo J. Schowalter, Robert T. Bondokov, James R. Grandusky
  • Patent number: 11387219
    Abstract: A power semiconductor module has a first and second intermediate circuit rail, an AC potential rail and with a packaged first and second power semiconductor switch. The respective power semiconductor switch has a first and second load current terminal and a control terminal, wherein the first power semiconductor switch is between the first intermediate circuit rail and the AC potential rail and the second power semiconductor switch is between the second intermediate circuit rail and the AC potential rail. The first load terminal of the first power semiconductor switch is contacted to the first intermediate circuit rail and the second load terminal of the first power semiconductor switch is electrically conductively contacted to the AC potential rail.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: July 12, 2022
    Assignee: SEMIKRON ELEKTRONIK GMBH & CO. KG
    Inventors: Martin Kraus, Klaus Benkert