Abstract: According to one embodiment, an electronic apparatus including a first substrate comprising a first conductive layer; a second substrate which is opposed to the first conductive layer and is separated from the first conductive layer, the second substrate including: a second conductive layer, and a first hole penetrating the second substrate; and a connecting material which electrically connects the first conductive layer and the second conductive layer via the first hole, wherein the second conductive layer is located on the second substrate on a side opposite to a side that is opposed to the first conductive layer.

Abstract: A method of making a thin film transistor, the method includes: providing a semiconductor layer; arranging a first photoresist layer, a nanowire structure, a second photoresist layer on the semiconductor layer, wherein the nanowire structure includes a single nanowire; forming one opening in the first photoresist layer and the second photoresist layer to form an exposed surface, wherein a part of the nanowire is exposed and suspended in the opening; depositing a conductive film layer on the exposed surface using the nanowire structure as a mask, wherein the conductive film layer defines a nano-scaled channel, and the conductive film layer is divided into two regions, one region is used as a source electrode, and the other region is used as a drain electrode; forming an insulating layer on the semiconductor layer to cover the source electrode and the drain electrode, and locating a gate electrode on the insulating layer.

Abstract: A method for forming a FinFET device structure is provided. The method for forming a FinFET device structure includes forming a fin structure over a substrate, and forming a source/drain (S/D) structure over the fin structure. The method for forming a FinFET device structure also includes forming an inter-layer dielectric (ILD) structure covering the S/D structure, and forming a gate structure over the fin structure and adjacent to the S/D structure. The method for forming a FinFET device structure further includes forming a first hard mask layer over the gate structure, and forming a second hard mask layer over the first hard mask layer. In addition, the method for forming a FinFET device structure includes etching the ILD structure to form an opening exposing the S/D structure. The opening and a recess in the second hard mask layer are formed simultaneously.

Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.

Abstract: A memory layout structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with all storage units on a corresponding active area, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.

Abstract: A method and a device for forming a highly dielectric metal oxide layer. The method includes repeatedly causing a plasma-off period and a plasma-on period while an organic metal compound and an oxidizing agent are continuously injected into a chamber. One cycle includes one plasma-off period and one plasma-on period. During the plasma-off period, a physical and chemical adsorption layer including an organic metal compound and a plurality of atomic layers is formed on a substrate. During the plasma-on period, a metal oxide layer that is thicker than two atomic layers is formed by a chemical reaction of metal atoms in the physical and chemical adsorption layer and oxygen atoms in the oxidizing agent.

Abstract: A catalyst is imparted selectively to a plateable material portion 32 by performing a catalyst imparting processing on a substrate W having a non-plateable material portion 31 and the plateable material portion 32 formed on a surface thereof. Then, a hard mask layer 35 is formed selectively on the plateable material portion 32 by performing a plating processing on the substrate W. The non-plateable material portion 31 is made of SiO2 as a main component, and the plateable material portion 32 is made of a material including, as a main component, a material containing at least one of a OCHx group and a NHx group, a metal material containing Si as a main component, a material containing carbon as a main component or a catalyst metal material.

Abstract: A semiconductor structure includes a source region, a drain region, a channel region located between the source region and the drain region, a gate stack structure including a gate dielectric and a gate electrode that overlies the gate dielectric, such that a first gap region is present between an area of the source region and an area of the gate electrode in a plan view and a second gap region is present between an area of the drain region and the area of the gate electrode in the plan view, a contact-level dielectric layer overlying the source region and the drain region and laterally surrounding the gate stack structure, and at least one assist-field metallic plate located vertically above a top surface of the gate electrode and having an areal overlap with at least one of the first gap region and the second gap region in the plan view.

Abstract: A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars.

Abstract: A semiconductor device may include a semiconductor substrate, an insulator film covering a part of an upper surface of the substrate, and a gate electrode opposing the upper surface via the insulator film. In the semiconductor substrate, a drift layer extending through a body layer to the upper surface opposes the gate electrode via the insulator film. The insulator film extends from the upper surface of the semiconductor substrate to an upper surface of the gate electrode by passing between the gate electrode and an upper electrode, and defines an opening at the upper surface of the gate electrode. A side surface of the opening of the insulator film is entirely located outside a volume space consisting of all straight lines that passes through the opposing surface of the drift layer at angle of 45 degrees to the opposing surface.

Abstract: A bonded structure is disclosed. The bonded structure includes a first element and a second element that is bonded to the first element along a bonding interface. The bonding interface has an elongate conductive interface feature and a nonconductive interface feature. The bonded structure also includes an integrated device that is coupled to or formed with the first element or the second element. The elongate conductive interface feature has a recess through a portion of a thickness of the elongate conductive interface feature. A portion of the nonconductive interface feature is disposed in the recess.

Abstract: A package structure is provided. The package structure includes a dielectric layer on a die, a RDL structure and a conductive terminal. The RDL structure comprises a redistribution layer in and on the dielectric layer. The redistribution layer comprises a via and a conductive plate. The via is located in and penetrating through the dielectric layer to be connected to the die. The conductive plate is on the via and the dielectric layer, and is connected to the die through the via. The conductive terminal is electrically connected to the die through the RDL structure. The via is ring-shaped.

Abstract: An organic photoelectronic device includes a first electrode and a second electrode facing each other, and first and second photoelectronic conversion layers between the first electrode and the second electrode. The first and second photoelectronic conversion layers include a p-type semiconductor and an n-type semiconductor. The first photoelectronic conversion layer has a first composition ratio (p1/n1) of the p-type semiconductor relative to the n-type semiconductor, the second photoelectronic conversion layer has a second composition ratio (p2/n2) of the p-type semiconductor relative to the n-type semiconductor, and the first composition ratio (p1/n1) is greater than the second composition ratio (p2/n2).

Abstract: The present embodiments provide systems, processes and/or methods of controlling irrigation. In some embodiments, methods are provided that receive (4112) water usage information corresponding to a first volumetric water usage at a site location having an irrigation controller (130), wherein the first volumetric water usage corresponds to volumetric water usage from a beginning of a budget period of time to a first time within the budget period of time; determine (4114) automatically whether a volumetric water budget at the site location will be met for the budget period of time based on at least the first volumetric water usage, the volumetric water budget corresponding to a specified volume of water for use during the budget period of time; determine (4116) automatically, in the event the volumetric water budget will not be met, an adjustment to the irrigation by the irrigation controller; and output (4118) signaling to effect the adjustment.

Abstract: A method of fabricating a connection structure is disclosed. The method includes providing a substrate that has a top surface and includes a set of pads for soldering, each of which has a pad surface exposed from the top surface of the substrate. The method also includes applying a surface treatment to a part of the top surface of the substrate close to the pads and the pad surface of each pad so as to make at least the part of the top surface and the pad surfaces of the pads rougher.

Abstract: A semiconductor device includes: a second semiconductor layer in a surface layer of a first semiconductor layer; a third semiconductor layer in a surface layer of the second semiconductor layer; a first trench penetrating the second semiconductor layer and the third semiconductor layer to reach an inside of the first semiconductor layer; a second trench penetrating, from an upper surface of the first semiconductor layer, the third semiconductor layer to reach an inside of the second semiconductor layer; and a fourth semiconductor layer in contact with a bottom of the second trench.

Abstract: A display apparatus includes a substrate including a display area where a plurality of pixels are provided and a non-display area surrounding the display area, an encapsulation layer including an inorganic layer and an organic layer and covering the display area, a dam disposed in the non-display area to surround the display area and to block a flow of the organic layer, a pad disposed in one edge of the non-display area and spaced apart from the dam in the non-display area, an auxiliary buffer layer spaced apart from the dam and disposed in the non-display area to overlap an end of the inorganic layer, a power auxiliary line disposed between the dam and the auxiliary buffer layer and electrically connected to the pad to receive a voltage from the pad, and a crack detection line spaced apart from the power auxiliary line and electrically connected to the pad.

Abstract: Provided is a semiconductor device manufacturing method which can suppress the occurrence of positional deviation or inclination of a semiconductor element when the semiconductor element is fixed so as to be sandwiched-between two insulating substrates. The semiconductor device manufacturing method includes: obtaining a laminated body in which a semiconductor element is temporarily adhered on a first electrode formed on a first insulating substrate with a first pre-sintering layer sandwiched therebetween; temporarily adhering the semiconductor element on a second electrode formed on a second insulating substrate with a second pre-sintering layer sandwiched therebetween, the second pre-sintering layer being provided on a side opposite to the first pre-sintering layer, to obtain a semiconductor device precursor; and simultaneously heating the first pre-sintering layer and the second pre-sintering layer, to bond the semiconductor element to the first electrode and the second electrode.

Abstract: A semiconductor memory device includes lower electrodes, each of the lower electrodes surrounding an inner space, an upper support layer on top surfaces of the lower electrodes, the upper support layer being on the inner spaces surrounded by the lower electrodes, and an upper electrode on the upper support layer, the upper electrode filling first and second regions, the second region penetrating the upper support layer, and the first region extending from the second region into between the lower electrodes. Each of the lower electrodes includes a first portion overlapping with the first region, a top surface of the first portion being exposed by the upper support layer, and a second portion covered by the upper support layer, a top surface of the second portion being in contact with the upper support layer.

Abstract: A semiconductor device having high reliability is obtained. A semiconductor device includes a semiconductor substrate, a first gate interconnection, a second gate interconnection, a first metal portion, an insulating member, and a second metal portion. The first gate interconnection and the second gate interconnection are disposed on a main surface of the semiconductor substrate with an interval therebetween. The first metal portion is formed on the first gate interconnection and the second gate interconnection. The first metal portion has a top surface located opposite to the semiconductor substrate at a region between the first gate interconnection and the second gate interconnection. A recess is formed in the top surface. The insulating member fills at least a portion of the recess. The second metal portion extends from an upper surface of the insulating member onto the top surface of the first metal portion.