Abstract: In some embodiments, the present disclosure relates to a memory structure. The memory structure has a source region and a drain region disposed within a substrate. A select gate disposed over the substrate between the source region and the drain region. A ferroelectric random access memory (FeRAM) device is disposed over the substrate between the select gate and the source region. The FeRAM device includes a ferroelectric material arranged between the substrate and a conductive electrode.

Abstract: A plasma processing method includes a gas supply step and a film forming step. In the gas supply step, a gaseous mixture containing a compound gas containing a silicon element and a halogen element, an oxygen-containing gas, and an additional gas containing the same halogen element as the halogen element contained in the compound gas and no silicon element is supplied into a chamber. In the film forming step, a protective film is formed on a surface of a member in the chamber by plasma of the gaseous mixture supplied into the chamber.

Abstract: A method for fabricating a semiconductor device includes: forming a plurality of bit line structures over a semiconductor substrate; forming a line-type opening between the bit line structures; forming a sacrificial spacer on both sidewalls of the line-type opening; forming a line-type plug filling the line-type opening over the sacrificial spacer; forming a plurality of plug isolation openings that expose the sacrificial spacer by etching a portion of the line-type plug in a direction crossing the bit line structures; forming a plurality of air gaps by removing the exposed sacrificial spacer; removing a remaining line-type plug below the plug isolation openings to form a plurality of island-type plugs; and forming a plug isolation layer inside the plug isolation openings to isolate neighboring island-type plugs from each other.

Abstract: A three-dimensional semiconductor device is provided including a gate electrode disposed on a substrate and having a pad region, a cell vertical structure passing through the gate electrode, a dummy vertical structure passing through the pad region, and a gate contact plug disposed on the pad region. The cell vertical structure includes a cell pad layer disposed on a level higher than that of the gate electrode and a cell channel layer opposing the gate electrode, the dummy vertical structure includes a buffer region formed of a material different from that of the cell pad layer and a dummy channel layer formed of a material the same as that of the cell channel layer, and at least a portion of the buffer region is located on the same plane as at least a portion of the cell pad layer.

Abstract: Structures that include a field effect-transistor and methods of forming a structure that includes a field-effect transistor. A first field-effect transistor includes a first source/drain region, and a second field-effect transistor includes a second source/drain region. A first contact is arranged over the first source/drain region, and a second contact is arranged over the second source/drain region. A portion of a dielectric layer, which is composed of a low-k dielectric material, is laterally arranged between the first contact and the second contact.

Abstract: A display substrate, a method of manufacturing the same and a display device are provided. The display substrate includes: a base substrate including an emission area and a transmission area; an electroluminescent device on the base substrate, the electroluminescent device including a first electrode in the emission area; a thin film transistor for controlling the electroluminescent device, the thin film transistor including an active layer; and a conductive member on the base substrate. The conductive member electrically connects the first electrode of the electroluminescent device with the active layer, the conductive member includes a contact portion in contact with the active layer, and the contact portion is located in the transmission area.

Abstract: The present disclosure provides a field of display technologies, and in particular, to a LTPS substrate and a fabricating method thereof, a thin film transistor thereof, an array substrate thereof, and a display device thereof. The LTPS substrate, able to be used for the fabrication of a thin film transistor, includes a light shielding layer, the light shielding layer mainly composed of amorphous silicon doped with a lanthanide element. The present disclosure mainly employs an amorphous silicon film layer doped with the lanthanide element as the light shielding layer of the LTPS substrate, which not only ensures the light shielding efficiency but also reduces the production process, and further prevents the occurrence of the H explosion problem due to H exuding during the ELA process.

Abstract: An organic light emitting display (OLED) device includes a substrate having a display region and a peripheral region at least partially surrounding the display region. An insulating layer structure is disposed on the substrate within both the display region and the peripheral region. The insulating layer structure includes a groove in the peripheral region. A plurality of pixel structures is disposed in the display region on the insulating layer structure. A block structure is disposed in the peripheral region so as to at least partially overlap the groove of the insulating layer structure. The block structure at least partially fills the groove of the insulating layer structure.

Abstract: Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include a substrate including first and second regions, first active fins extending in a first direction on the first region, second active fins extending parallel to the first active fins on the second region, and single diffusion break regions between two first active fins. Single diffusion break regions may be spaced apart from each other in the first direction. The semiconductor devices may also include a lower diffusion break region between two second active fins and extending in a second direction that is different from the first direction and upper diffusion break regions on the lower diffusion break region. The upper diffusion break regions may be spaced apart from each other in the first direction, and each of the upper diffusion break regions may overlap the lower diffusion break region.

Abstract: A semiconductor device has a substrate. An electrical component is disposed over a surface of the substrate. An encapsulant is deposited over the electrical component and substrate. A portion of the surface of the substrate remains exposed from the encapsulant. A shielding layer is formed over the encapsulant. A portion of the shielding layer is removed to expose the portion of the surface of the substrate.

Abstract: Discussed is an organic light emitting diode (OLED) lighting apparatus including a substrate; an auxiliary wiring disposed on the substrate; a protective layer configured to cover the auxiliary wiring; a first electrode disposed between the auxiliary wiring and the protective layer to be in direct contact with the auxiliary wiring, the first electrode including a first layer and a second layer, the first layer having a first resistance, and the second layer being configured to cover the first layer and the protective layer and having a second resistance higher than the first resistance; an organic light emitting layer disposed on the first electrode; and a second electrode disposed on the organic light emitting layer.

Abstract: An embodiment discloses a semiconductor device including a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer; a first electrode electrically connected with the first conductive semiconductor layer; and a second electrode electrically connected with the second conductive semiconductor layer, and a semiconductor device package including the same. The second conductive semiconductor layer includes a first surface on which the second electrode is disposed. The second conductive semiconductor layer has a ratio of a second shortest distance W2, which is a distance from the first surface to a second point, to a first shortest distance W1, which is a distance from the first surface to a first point, (W2:W1) ranging from 1:1.25 to 1:100.

Abstract: A method for producing a component having a semiconductor body includes providing the semiconductor body including a radiation passage surface and a rear side facing away from the radiation passage surface, wherein the semiconductor body comprises on the rear side a connection location for the electrical contacting of the semiconductor body, providing a composite carrier including a carrier layer and a partly cured connecting layer, applying the semiconductor body on the composite carrier, such that the connection location penetrates into the partly cured connecting layer, curing the connecting layer to form a solid composite, applying a molded body material on the composite carrier after curing the connecting layer, wherein the molded body covers side surfaces of the semiconductor body, forming a cutout through the carrier layer and the connecting layer in order to expose the connection location, and filling the cutout with an electrically conductive material.

Abstract: A manufacturing method of a display panel is provided and includes providing a substrate; and forming a buffer layer, a polysilicon layer, a gate electrode, an interlayer insulating layer, a first transparent electrode layer, a source electrode and drain electrode line, and a touch control line on the substrate in sequence. A masking process is omitted using a planarization layer as a photoresist layer of the interlayer insulating layer. One more masking process is omitted by forming the pixel electrode, the source electrode and drain electrode line and the touch control line in a same masking process.

Abstract: A method of forming a semiconductor structure includes forming a dielectric layer surrounding contacts over a top surface and bevel edge of a substrate, forming a sacrificial buffer layer over the dielectric layer, removing portions of the sacrificial buffer layer formed over the dielectric layer on the top surface of the substrate, and patterning device structures including one or more metal layers over the contacts, wherein patterning the device structures removes portions of the metal layers formed over the top surface of the substrate leaving the metal layers on the bevel edge. The method also includes forming an encapsulation layer and performing a bevel dry etch to remove the encapsulation layer and the metal layers on the bevel edge. The bevel dry etch damages the sacrificial buffer layer on the bevel edge underneath the metal layers. The method further includes removing the damaged sacrificial buffer layer from the bevel edge.

Abstract: A support substrate has a face above which at least one electronic component is fixed. A peripheral area of the face includes an annular local metal layer. An encapsulating cover for the electronic component includes a peripheral wall having an end edge that is mounted above the peripheral area. The annular metal local layer includes, at the periphery thereof, a series of spaced-apart teeth with notches formed therebetween. The teeth extend as far as the peripheral edge of the support substrate.

Abstract: A memory device is provided that includes a bilayer nanosheet channel layer including a silicon (Si) layer and a silicon germanium (SiGe) layer; and a common gate structure for biasing each of the silicon layer and the silicon germanium layer of the bilayer nanosheet channel layer to provide one of the silicon layer and the silicon germanium layer is biased in accumulation and one of the first layer and the second layer biased in inversion. The memory devices also includes a floating body region on a front face or rear face of the bilayer nanosheet channel layer.

Abstract: An array substrate, a display panel, and a display device. The array substrate has a display area and a non-display area surrounding the display area. The array substrate further includes a plurality of signal lines located in the display area, a plurality of test signal lines and a plurality of test control transistors located in the non-display area and respectively corresponding to the plurality of signal lines. Each of the signal lines is connected to a respective one of the test signal lines by a respective one of the test control transistors. The plurality of test control transistors each have a channel width-to-length ratio between 10 and 200.

Abstract: Disclosed herein is a method of forming a semiconductor structure. The method includes the steps of: forming a first dielectric layer having a first through hole on a precursor substrate, in which the first through hole passes through the first dielectric layer; filling a sacrificial material in the first through hole; forming a second dielectric layer having a second through hole over the first dielectric layer, in which the second through hole exposes the sacrificial material in the first through hole, and the second through hole has a bottom width less than a top width of the first through hole; removing the sacrificial material after forming the second dielectric layer having the second through hole; forming a barrier layer lining sidewalls of the first and second through holes; and forming a conductive material in the first and second through holes.

Abstract: A semiconductor device has a substrate, a first dielectric fin, and an isolation structure. The substrate has a first semiconductor fin. The first dielectric fin is disposed over the substrate and in contact with a first sidewall of the first semiconductor fin, in which a width of the first semiconductor fin is substantially equal to a width of the first dielectric fin. The isolation structure is in contact with the first semiconductor fin and the first dielectric fin, in which a top surface of the isolation structure is in a position lower than a top surface of the first semiconductor fin and a top surface of the first dielectric fin.