Abstract: An improved method and system for laser doping a semiconductor material is described. In the invention, phosphorous nitride is used as a dopant source. The phosphorous nitride is brought into close proximity with a region of the semiconductor to be doped. A pulse of laser light decomposes the phosphorous nitride and briefly melts the region of semiconductor to be doped to allow incorporation of dopant atoms from the phosphorous nitride into the semiconductor.

Abstract: A method of forming a semiconductor device by placing a semiconductor substrate in a vacuum chamber and subjecting the semiconductor substrate (20) to a sub-atmospheric pressure, and depositing a layer (40) on the semiconductor substrate while maintaining the sub-atmospheric pressure. Deposition of the layer (40) is carried out by sequentially (i) flowing a first reactant into the vacuum chamber at a first flow rate, (ii) reducing flow of the first reactant into the vacuum chamber to a second flow rate, and (iii) increasing flow of the first reactant into the vacuum chamber to a third flow rate.

Abstract: A method of forming a gate device which includes an elongated projection on a substrate. The elongated projection protrudes from a surrounding area of the substrate and includes an access channel for the gate device. A first terminal and a second terminal are formed and coupled to the access channel in the elongated projection. A gate structure is operable to control the access channel to selectively couple the first terminal to the second terminal.

Abstract: A silicon on insulator (SOI) dynamic random access memory (DRAM) cell and array and method of manufacture. The memory cell includes a trench storage capacitor connected by a self aligned buried strap to a vertical access transistor. A buried oxide layer isolates an SOI layer from a silicon substrate. The trench capacitor is formed in the substrate and the access transistor is formed on a sidewall of the SOI layer. A polysilicon strap connected to the polysilicon plate of the storage capacitor provides a self-aligned contact to the source of the access transistor. Initially, the buried oxide layer is formed in the wafer. Deep trenches are etched, initially just through the SOI layer and the BOX layer. Protective sidewalls are formed in the trenches. Then, the deep trenches are etched into the substrate. The volume in the substrate is expanded to form a bottle shaped trench.

Abstract: A method of preventing formation of titanium oxide within a semiconductor device structure during a high temperature treatment of the device structure includes forming a passivation layer to preclude formation of titanium oxide at a titanium/oxide interface of a semiconductor device structure. The method includes providing a substrate assembly including at least an oxide region and forming a layer of titanium over a surface of the oxide region. The oxide region surface is treated with a plasma comprising nitrogen prior to forming the titanium layer so as to form a passivation layer upon which the titanium layer is formed. A thermal treatment is performed on the substrate assembly with the passivation layer substantially inhibiting diffusion of oxygen from the oxide layer during the thermal treatment of the substrate assembly. Generally, the passivation layer comprises SixOyNz.

Abstract: A semiconductor device capable of operating at a high speed or of having many functions. In this device, delamination of buried electrodes is prevented and thus high reliability is offered. The depth A of contact holes, the minimum linewidth R of a lower metallization layer, and the thickness B of the lower metallization layer satisfy relations given by (0.605/R)0.5<A<2.78−1.02B+0.172B2.

Abstract: There is provided a technique for forming an Ru film on the bottom of a deep hole with a considerable film thickness for the lower electrode of an information storage capacity element in order to improve the yield of manufacturing DRAMs. The Ru film is formed on the side wall and the bottom of a deep hole as material for preparing the lower electrode of an information storage capacity element to be produced there under the condition of a gasification flow rate ratio of the raw materials ((Ru(C2H5C5H4)2/O2) is not less than 10% Then, the ratio of the film thickness of the Ru film on the bottom “b” of the hole to the largest film thickness “a” of the Ru film in the hole is not less than 50%.

Abstract: On manufacturing a glass substrate for an information recording medium, after a principal surface of the glass substrate is polished, sulfuric acid-cleaning of the principal surface is carried out so that the glass substrate has surface roughnesses Ra and Rmax satisfying Ra=0.1-0.7 nm and Rmax/Ra<20 as measured by an inter-atomic force microscope (AFM), where Ra is representative of a center-line-mean roughness and where Rmax is defined as a maximum height representative of a difference between a highest point and a lowest point.

Abstract: A process for forming a non-porous dielectric diffusion barrier layer on etched via and trench sidewall surfaces in a layer of porous low k dielectric material comprises exposing such etched surfaces to a plasma formed from one or more gases such as, for example, O2; H2; Ar; He; SiH4; NH3; N2; CHxFy, where x=1-3 and y=4-y; H2O; and mixtures of same, for a period of time sufficient to form from about 1 nanometer (nm) to about 20 nm of the non-porous dielectric diffusion barrier layer which prevents adsorption of moisture and other process gases into the layer of porous low k dielectric material, and prevents degassing from the porous low k dielectric material during subsequent processing.

Abstract: A method of measuring the thickness of an epitaxial layer is disclosed. The method is particularly useful in measuring the epitaxial layer with a doping concentration lower than or similar to the substrate on which the epitaxial layer is formed. The method uses a non-single crystal layer previously formed on the substrate before forming the epitaxial layer over the substrate so that the portion of the epitaxial layer on the non-single crystal layer will be polycrystal. To obtain the thickness of the epitaxial layer, thicknesses of the polycrystal layer and the non-single crystal layer as well as the thickness difference between the polycrystal layer plus the non-single crystal layer and the epitaxial layer are measured. The thickness of the epitaxial layer equals the result of the total thickness of the polycrystal layer plus the non-single crystal layer minus the thickness difference between the polycrystal layer plus the non-single crystal layer and the epitaxial layer.

Abstract: A semiconductor device and method of fabricating the same. The semiconductor device includes a first insulating film formed on a substrate and having a plurality of holes therein; a cavity formed under the first insulating film; an impurity region formed in the substrate and around the cavity; a second insulating film formed on portions of the first insulating film to fill the holes and a space between the cavity and the impurity region; a plurality of contact holes formed to expose certain portions of the impurity region; and a plurality of wiring layers formed to be in contact with the impurity region through the contact holes.

Abstract: Methods and semiconductor structures are provided for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices. A bulk silicon substrate layer is provided that defines one power distribution rail. A high energy deep oxygen implant is performed to create a deep buried oxide layer and a first intermediate silicon layer. The deep buried oxide layer is disposed between the bulk silicon substrate layer and the first intermediate silicon layer. The first intermediate silicon layer defines another power distribution rail. A lower energy oxygen implant is performed to create a shallow buried oxide layer and a second intermediate silicon layer. The shallow buried oxide layer is disposed between the first intermediate silicon layer and the second intermediate silicon layer. A connection to the bulk silicon substrate layer is formed without making electrical connection to the intermediate silicon layers.

Abstract: A little amount of nickel is introduced into an amorphous silicon film formed on a glass substrate to crystallize the amorphous silicon film by heating. In this situation, nickel elements remain in a crystallized silicon film. An amorphous silicon film is formed on the surface of the crystallized silicon film and then subjected to a heat treatment. With this heat treatment, the nickel elements are diffused in the amorphous silicon film, thereby being capable of lowering the concentration of nickel in the crystallized silicon film.

Abstract: In an active matrix substrate, a glass substrate is provided with TFTs having gate electrodes connected to scanning lines also provided on the glass substrate. The glass substrate is further provided with auxiliary capacitance lines, formed on the same layer as the scanning lines. Further, pixel electrodes connected to drain electrodes of the TFTs are formed on the same layer as signal lines connected to source electrodes of the TFTs. An insulating layer is provided between the layer forming the signal lines and pixel electrodes and the layer forming the drain and source electrodes. Since the insulating film is present between the signal lines and the scanning and auxiliary capacitance lines, influence on the auxiliary capacitance value can be reduced, as can a signal line capacitance value. As a result, even when the auxiliary capacitance value is increased, the signal line capacitance value remains small.

Abstract: A silicided region (11a) is formed in part of a surface of a gate electrode (3a) which is far from a storage node when a diffusion region (7a) is connected to a bit line and a diffusion region (8a) is connected to the storage node. A silicided region (12a) is formed in a surface of the diffusion region (7a) connected to the bit line. A MOSFET which suppresses a leakage current from the storage node to the gate electrode and decreases the resistance of the diffusion region connected to the bit line and the resistance of said gate electrode is provided.

Abstract: A polysilicon thin film transistor (poly-Si TFT) with a self-aligned lightly doped drain (LDD) structure has a transparent insulating substrate; a buffering layer formed on the transparent insulating substrate; a polysilicon layer formed on the buffering layer and having a channel region, an LDD structure surrounding the channel region, and a source/drain region surrounding the LDD structure; a gate insulating layer formed on the polysilicon layer; a gate layer formed on the gate insulating layer and positioned over the channel region; an insulating spacer formed on the sidewall of the gate layer and positioned over the LDD structure; and a subgate gate layer formed on the insulating spacer.

Abstract: In a patterning process of a semiconductor device having inverted stagger type TFTs, a normal photolithography step using diazo naphthoquinone (DNQ)-Novolac resin based positive photo resist is applied, and a problem of the area dependency of the photo resist pattern side wall taper angle may occur. The problem is critical for the reason of influence on variation of an etching shape in a dry-etching step. The present invention has an object to solve the above problem. In a photolithography step, which is patterning step of a semiconductor device having inverted stagger type TFTs, by adjusting a pre-bake temperature or a PEB (post-exposure-bake) temperature, and positively performing evacuation of solvent in a state of a photo resist film, the volume contraction by evacuation of solvent at the post-bake is reduced, and the problem of the area dependency of the photo resist pattern side wall taper angle is solved, which is deformation due to the volume contraction.

Abstract: The invention relates to a method for fabricating in particular a TMR element for use in a MRAM, wherein a mask is arranged on a substrate and structured in such a manner that it shadows but does not cover a surface region of the substrate, and wherein material of the structure which is to be fabricated is then deposited on the substrate in a directed deposition process. The invention also relates to a component with a micro-technical structure which has been fabricated in this manner.

Abstract: A stabilized GMR device includes a GMR stack having a first and a second edge. Stabilization means are positioned adjacent to the first and the second edge of the GMR stack for stabilizing the GMR stack. The GMR stack includes a first layer of ferromagnetic material and a second layer of ferromagnetic material. A spacer layer is positioned between the first and the second ferromagnetic layers. A buffer layer is positioned adjacent to the first magnetic layer and a cap layer is positioned adjacent to the second ferromagnetic layer. The stabilization means include a first coupler layer positioned adjacent to the first edge of the GMR stack and a second coupler layer positioned adjacent to the second edge of the GMR stack. The stabilization means also include a first ferromagnetic layer positioned adjacent to the first coupler layer and a second ferromagnetic layer positioned adjacent to the second coupler layer.

Abstract: An integrated circuit and manufacturing method therefor is provided for an integrated circuit on a semiconductor substrate grated circuit having a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. A barrier layer lines the opening, and a first conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A shunt layer is in the via opening above the conductor core. A barrier layer lines the second channel and via opening over the shunt layer and the second dielectric layer. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via.