Abstract: A method for placing nitride laser diode arrays on a thermally conducting substrate is described. The method uses an excimer laser to detach the nitride laser diode from the sapphire growth substrate after a thermally conducting substrate has been bonded to the side opposite the sapphire substrate.

Abstract: An address element, including a polysilicon resistor functioning as a heating element and blocking diode preventing sneak current to unaddressed elements, is selectively addressed using row and column address lines in a thin film structure having a minimum number of address lines and a minimum number of layers. The resistor heater element is well suited for igniting a fuel cell such as a fuel cell in an array of fuel cells disposed in a thin film microthruster.

Abstract: A process for fabricating a tapered trench on a silicon substrate. The process comprises the steps of forming an initial trench in the substrate and implanting nitrogen ions on the initial trench side walls. More nitrogen ions are implanted adjacent the exposed surface of the substrate than adjacent the trench bottom. Finally, the initial trench side walls are oxidized to create the tapered shape.

Abstract: To expose interconnection patterns of a target wring width by detecting the focus position variation and the sensitivity variation separately to correct the exposure condition without previous calculation of the correction magnitude which is optimal for exposure of the wring width of interconnection patterns of the target size of a semiconductor device, the first exposure management pattern 18 having interconnection patterns which are disposed with a certain interval and disposed so that the variation in the exposure quantity on the semiconductor substrate affects the interconnection width but the variation in focus position which occurs when the semiconductor substrate is exposed does not affect the interconnection width and the second exposure management pattern 16 having interconnection patterns which are disposed with a certain interval different from that of the first exposure management pattern and disposed so that both focus variation and exposure quantity variation affect the interconnection width are

Abstract: A plurality of first contact holes reaching an n+-type semiconductor area used as the source of a MISFET employed in a logic-DRAM mixture LSI and a plurality of second contact holes reaching another n+-type semiconductor area used as the drain of the MISFET are bored through an insulation layer created over a gate electrode of the MISFET. A conductive film on the same layer as a bit line shunts the n+-type semiconductor area used as the source through the first contact holes. Another conductive film shunts the n+-type semiconductor area used as the drain through the second contact holes.

Abstract: A modified flow for ASIC place an route software flow which allows incorporation into the flow, a process for tracking the locations of substrate contacts and well-ties within and outside the boundaries of placed cells and generating required supplemental placements, making possible an efficient use of silicon chip area expended in the adequate placement of substrate contacts and well-ties.

Abstract: A silicon on insulator (SOI) field effect transistor (FET) structure is formed on a conventional bulk silicon wafer. The structure includes an electrical coupling between the channel region of the FET with the bulk silicon substrate to eliminate the floating body effect caused by charge accumulation in the channel regions due to historical operation of the FET. The method of forming the structure includes isolating the FET active region from other structures in the silicon substrate by forming an insulating trench about the perimeter of the FET and forming an undercut beneath the active region to reduce or eliminate junction capacitance between the source and drain regions and the silicon substrate.

Abstract: Semiconductor packages which are prepared by forming circuit substrates, mounting IC chips on the circuit substrates, encapsulating the IC chips on the circuit substrates with resin, and forming electrodes, are attached to a standard member. After this attaching step, the semiconductor packages are subjected to a cutting step where the semiconductor packages are diced into a plurality of circuit substrates.

Abstract: A TFT of the present invention includes an insulating substrate, a first conductive film layer which is to be a gate electrode provided on the insulating substrate, a first insulating film layer which is to be a gate insulating film layer provided on the first conductive film layer, a non-doped semiconductor layer formed on the first insulating film layer, and a second conductive film layer which is to be a source electrode formed on a source region of the semiconductor layer and a drain electrode formed on a drain region of the semiconductor, wherein a junction is formed by implanting an n-type impurity in the source region of the semiconductor layer and the drain region of the semiconductor.

Abstract: Method for forming a semiconductor device having an capacitor, where the capacitor is in-laid in a cavity formed in the semiconductor substrate and part of a high density memory. One embodiment first forms a bottom electrode in the cavity and then fills the cavity with a sacrificial layer to allow chemical mechanical polishing (CMP) of at least one of the capacitor electrodes. After removing portions of the bottom electrode and portions of the sacrificial layer, a dielectric layer is formed. A top electrode is then formed over the dielectric layer. The dielectric layer so formed isolates the bottom electrode from the top electrode preventing shorting and leakage currents. In one embodiment, a single top electrode layer is formed for multiple bottom electrodes, reducing the complexity of the memory circuit.

Abstract: A capacitor having high capacitance using a silicon-containing conductive layer as a storage node, and a method for forming the same, are provided. The capacitor includes a storage node, an amorphous Al2O3 dielectric layer, and a plate node. The amorphous Al2O3 layer is formed by a method in which reactive vapor phase materials are supplied on the storage node, for example, an atomic layered deposition method. Also, the storage node is processed by rapid thermal nitridation before forming the amorphous Al2O3 layer. The amorphous Al2O3 layer is densified by annealing at approximately 850° C. after forming a plate node, to thereby realize the equivalent thickness of an oxide layer which approximates a theoretical value of 30 Å.

Abstract: A gate wire including a plurality of gate lines and gate electrodes in the display area, and gate pads in the peripheral area is formed on a substrate having a display area and a peripheral area. A gate insulating layer, a semiconductor layer, an ohmic contact layer and a conductor layer are sequentially deposited, and the conductor layer and the ohmic contact are patterned to form a data wire including a plurality of data lines, a source electrode and a drain electrode of the display area and data pads of the peripheral area, and an ohmic contact layer pattern thereunder. A passivation layer is deposited and a positive photoresist layer is coated thereon. The photoresist layer is exposed to light through one or more masks having different transmittance between the display area and the peripheral area. The photoresist layer is developed to form a photoresist pattern having the thickness that varies depending on the position.

Abstract: A little amount of nickel is introduced into an amorphous silicon film formed on a glass substrate to crystallize the amorphous silicon film by heating. In this situation, nickel elements remain in a crystallized silicon film. An amorphous silicon film is formed on the surface of the crystallized silicon film and then subjected to a heat treatment. With this heat treatment, the nickel elements are diffused in the amorphous silicon film, thereby being capable of lowering the concentration of nickel in the crystallized silicon film.

Abstract: A mounting structure includes a laminated ceramic capacitor mounted on a mounting substrate. The laminated ceramic capacitor includes a main body chip made by a ceramic dielectric, internal layer electrodes, and pair of terminal electrodes. The mounting substrate is made by alumina substrate, and has a pair of substrate electrodes made by copper plating. The laminated ceramic capacitor is mounted on the mounting substrate by using an Ag paste. Here, the substrate electrode is set to be smaller than the Ag paste. That is, the Ag paste is extruded from the terminal electrodes and the substrate electrode so as to contact to both of the main body chip and the mounting substrate. Because the Ag paste has a high adhesive strength compared to that when it is bonded with a metal, total adhesive strength can be improved. Consequently, the reliability of mounting can be improved.

Abstract: A self-aligned contact process. A substrate is provided. A gate including a polysilicon layer and a metal silicide layer is formed on the substrate. A cap layer is formed on the gate to protect the gate. A first spacer is formed on the sidewall of the gate. A first ion implantation is performed using the gate and the first spacer as a first mask to form lightly doped regions in the substrate. A conformal liner layer is formed on the cap layer, the first spacer and the substrate. An insulating layer is formed on the conformal liner layer. A part of the insulating layer and a part of the liner layer are removed until exposing the cap layer. A part of the liner layer remaining on the first spacer and a part of the insulating layer remaining on the remaining liner layer are used as a second spacer. A second ion implantation is performed to form source/drain regions with lightly doped drain (LDD) structures in the substrate beside the second spacer.

Abstract: A method and semiconductor structure are provided for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors. A bulk silicon substrate is provided. A deep ion implant layer is implanted to reside below an oxide insulator. An oxygen implant layer is implanted while applying a mask to block the oxygen implant layer in selected regions. The selected regions provide for body contact for the SOI transistors. Holes are formed extending into the deep ion implant layer and the bulk silicon substrate. The holes are filled with an electrically conductive material to create stud contacts to the deep ion implant layer and the bulk silicon substrate.

Abstract: A method of determining the thickness of a layer on a substrate where the layer is deposited during a semiconductor manufacturing process. The substrate is weighed a first time. The layer is deposited on the substrate and the substrate is weighed a second time. The thickness of the layer is calculated using the difference between the second weighing and the first weighing.

Abstract: A method for producing a semiconductor device, comprises the steps of: introducing a plurality of semiconductor element supporting substrates or semiconductor elements into a conductive-ball attaching system for collectively attaching conductive balls onto the supporting substrates or semiconductor elements; detecting the position of a defective substrate or defective semiconductor element of the introduced semiconductor element supporting substrates or semiconductor elements, or an undesired position, at which it is not necessary to load the conductive balls; vacuum holding a plurality of conductive balls, which are stored in the conductive-ball attaching system, by conductive-ball holding means; and selectively attaching the plurality of conductive balls, which are vacuum-held by the conductive-ball holding means, onto a desired supporting substrate or semiconductor element of the supporting substrates or semiconductor elements introduced into the conductive-ball attaching system, wherein the conductive-bal

Abstract: A method for fabricating semiconductor components, such as BGA packages, chip scale packages, and multi chip modules, includes the steps of cutting decals from ribbons of adhesive tape, and then attaching a semiconductor die to a substrate using the decals. A system for performing the method includes a tape cutting apparatus configured to cut the decals from the tape without wasted tape, and then to apply the cut decals to the substrate. A first finished dimension (e.g., width) of the decals is determined by a width of the tape, and a second finished dimension (e.g., length) of the decals is determined by indexing the tape through a selected distance. The tape cutting apparatus includes cutters configured to move through guide openings to cut and apply the decals to the substrate. The guide openings align the tape to the cutters, and also align the cut decals to the substrate. The system also includes a substrate handling apparatus configured to index and position the substrate relative to the guide openings.

Abstract: This is a semiconductor device made by using a film carrier tape and method of making the same, wherein the package size is close to the chip size and connection portions for electrodes of a semiconductor chip are not exposed. Electroplating is performed in a state where connection leads 24, plating leads 26 and plating electrodes 28 are all conductive, the connection leads being are formed within a region to be filled with a molding material 36 and being connected to electrodes 42 of a semiconductor chip 40 and pad portions 22, the plating leads 26 being connected to the connection leads 24, and plating electrodes 28 being connected to the plating leads 26. The connection portions 29 are punched out into the region to be filled with the molding material, the connection leads 24 and the electrodes 42 are connected, and the molding material 36 is poured in. The end surfaces of the connection leads 24 that are exposed from the holes 32 are also covered by the molding material 36 so as not to be exposed.