Patents Examined by Lawrence C Tynes, Jr.
  • Patent number: 11562963
    Abstract: According to various examples, a stacked semiconductor package is described. The stacked semiconductor package may include a package substrate. The stacked semiconductor package may also include a base die disposed on and electrically coupled to the package substrate. The stacked semiconductor package may further include a mold portion disposed on the package substrate at a periphery of the base die, the mold portion may include a through-mold interconnect electrically coupled to the package substrate. The stacked semiconductor package may further include a semiconductor device having a first section disposed on the base die and a second section disposed on the mold portion, wherein the second section of the semiconductor device may be electrically coupled to the package substrate through the through-mold interconnect.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: January 24, 2023
    Assignee: Intel Corporation
    Inventors: Chin Lee Kuan, Bok Eng Cheah, Jackson Chung Peng Kong, Sameer Shekhar, Amit Jain
  • Patent number: 11557520
    Abstract: A display device includes a pixel connected to a data line, a data pad connected to the data line, and a first test area. The first test area includes a test control line transmitting a test control signal, a test signal line transmitting a test signal, and a first switch connected to the data pad. The first switch includes a gate electrode connected to the test control line, first and second semiconductor layers overlapping the gate electrode, a source electrode connected to the first and second semiconductor layers, and a drain electrode spaced from the source electrode and connected to the first and second semiconductor layers. The source electrode and the drain electrode are connected to the test signal line and data pad, respectively. One of the first or second semiconductor layers includes an oxide semiconductor and the other of the first or second semiconductor layer includes a silicon-based semiconductor.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: January 17, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jihyun Ka, Wonkyu Kwak, Hansung Bae
  • Patent number: 11552468
    Abstract: An electrical device includes a first terminal structured to electrically connect to a power source; a second terminal structured to electrically connect to a load; a voltage sensor electrically connected to a point between the first and second terminals and being structured to sense a voltage at the point between the first and second terminals; a switch electrically connected between the first terminal and the second terminal; and a control unit structured to detect a power quality event in the power flowing between the first and second terminals based on the sensed voltage and to control a state of the switch based on the detected power quality event.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: January 10, 2023
    Assignee: EATON INTELLIGENT POWER LIMITED
    Inventors: Charles John Luebke, Birger Pahl, Steven Christopher Schmalz
  • Patent number: 11545428
    Abstract: A method of forming a metal-insulator-metal (MIM) capacitor with copper top and bottom plates may begin with a copper interconnect layer (e.g., Cu MTOP) including a copper structure defining the capacitor bottom plate. A passivation region is formed over the bottom plate, and a wide top plate opening is etched in the passivation region, to expose the bottom plate. A dielectric layer is deposited into the top plate opening and onto the exposed bottom plate. Narrow via opening(s) are then etched in the passivation region. The wide top plate opening and narrow via opening(s) are concurrently filled with copper to define a copper top plate and copper via(s) in contact with the bottom plate. A first aluminum bond pad is formed on the copper top plate, and a second aluminum bond pad is formed in contact with the copper via(s) to provide a conductive coupling to the bottom plate.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: January 3, 2023
    Assignee: Microchip Technology Incorporated
    Inventor: Yaojian Leng
  • Patent number: 11532603
    Abstract: The present invention discloses a display panel and a head mounted device. The display panel includes a substrate and a plurality of micro light emitting units. A first position and a second position are defined at an edge and a center of the substrate respectively. The micro light emitting units are arranged and disposed on the substrate. Any two of the micro light emitting units are disposed at the first position and the second position respectively. Wherein each micro light emitting unit defines a luminating top surface, and a reference angle is defined between each luminating top surface and a reference plane respectively. Wherein the reference angle defined between each luminating top surface and the reference plane gradually decreases from the first position to the second position, and the luminating top surface of the micro light emitting unit located at the second position is parallel to the reference surface.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: December 20, 2022
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Yi-Ching Chen, Pei-Hsin Chen, Yi-Chun Shih
  • Patent number: 11532508
    Abstract: An embodiment relates to a method for manufacturing a semiconductor device. The method includes providing a semiconductor body including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type interposed between the first semiconductor region and a first surface of the semiconductor body. The method further includes forming a first contact layer over the first surface of the semiconductor body. The first contact layer forms a direct electrical contact to the second semiconductor region. The method further includes forming a contact trench extending into the semiconductor body by removing at least a portion of the second semiconductor region. The method further includes forming a second contact layer in the contact trench. The second contact layer is directly electrically connected to the semiconductor body at a bottom side of the contact trench.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: December 20, 2022
    Assignee: Infineon Technologies AG
    Inventors: Holger Huesken, Frank Dieter Pfirsch
  • Patent number: 11532483
    Abstract: A method may include forming in a substrate a first array of a first material of first linear structures, interspersed with a second array of a second material, of second linear structures, the first and second linear structures elongated along a first axis. The method may include generating a chop pattern in the first layer, comprising a third linear array, interspersed with a fourth linear array. The third and fourth linear arrays may be elongated along a second axis, forming a non-zero angle of incidence with respect to the first axis. The third linear array may include alternating portions of the first and second material, while the fourth linear array comprises an array of cavities, arranged within the patterning layer. The method may include elongating a first set of cavities along the first axis, to form a first set of elongated cavities bounded by the first material.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: December 20, 2022
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventor: Sony Varghese
  • Patent number: 11532582
    Abstract: Semiconductor devices and methods of manufacture are described herein. The methods include forming a local organic interconnect (LOI) by forming a stack of conductive traces embedded in a passivation material, forming first and second local contacts over the passivation material, the second local contact being electrically coupled to the first local contact by a first conductive trace of the stack. The methods further include forming a backside redistribution layer (RDL) and a front side RDL on opposite sides of the LOI with TMVs electrically coupling the backside and front side RDLs to one another. First and second external contacts are formed over the backside RDL for mounting of semiconductor devices, the first and second external contacts being electrically connected to one another by the LOI. An interconnect structure is attached to the front side RDL for further routing. External connectors electrically coupled to the external contacts at the backside RDL.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun Yi Wu, Chen-Hua Yu
  • Patent number: 11515688
    Abstract: A device, such as a light-emitting device, e.g. a laser device, comprising: a plurality of group III-V semiconductor NWs grown on one side of a graphitic substrate, preferably through the holes of an optional hole-patterned mask on said graphitic substrate; a first distributed Bragg reflector or metal mirror positioned substantially parallel to said graphitic substrate and positioned on the opposite side of said graphitic substrate to said NWs; optionally a second distributed Bragg reflector or metal mirror in contact with the top of at least a portion of said NWs; and wherein said NWs comprise aim-type doped region and a p-type doped region and optionally an intrinsic region there between.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: November 29, 2022
    Assignee: Norwegian University of Science and Technology
    Inventors: Bjorn Ove Myking Fimland, Helge Weman, Dingding Ren
  • Patent number: 11508704
    Abstract: A display panel including a circuit board having first pads, a plurality of light emitting devices disposed on the circuit board and having second pads, at least one of the light emitting devices including a repaired light emitting device, and a metal bonding layer bonding the first pads and the second pads, in which the metal bonding layer of the repaired light emitting device has at least one of a thickness and a composition different from that of the metal bonding layer of the remaining light emitting devices.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: November 22, 2022
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Jong Hyeon Chae, Ik Kyu You, Seom Geun Lee, Seong Kyu Jang, Yong Woo Ryu
  • Patent number: 11508729
    Abstract: The present application provides a semiconductor die with decoupling capacitors and a manufacturing method of the semiconductor die. The semiconductor die includes first bonding pads, second bonding pads, bond metals and decoupling capacitors. The first bonding pads are coupled to a power supply voltage. The second bonding pads are coupled to a reference voltage. The bond metals are disposed on central portions of the first and second bonding pads. The decoupling capacitors are disposed under the first and second bonding pads, and overlapped with peripheral portions of the first and second bonding pads. The decoupling capacitors are in parallel connection with one another. First terminals of the decoupling capacitors are electrically connected to the first bonding pads, and second terminals of the decoupling capacitors are electrically connected to the second bonding pads.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: November 22, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wu-Der Yang
  • Patent number: 11508677
    Abstract: A semiconductor structure and a method of forming the same are provided. A method of manufacturing the semiconductor structure includes: providing a substrate; depositing a first dielectric layer over the substrate; attaching a waveguide to the first dielectric layer; depositing a second dielectric layer to laterally surround the waveguide; and forming a first conductive member and a second conductive member over the second dielectric layer and the waveguide, wherein the first conductive member and the second conductive member are in contact with the waveguide. The waveguide is configured to transmit an electromagnetic signal between the first conductive member and the second conductive member.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Huan-Neng Chen, Wen-Shiang Liao
  • Patent number: 11508722
    Abstract: A semiconductor device structure includes an isolation structure disposed in a semiconductor substrate. The semiconductor device structure also includes a gate electrode and a resistor electrode disposed in the semiconductor substrate. The isolation structure is disposed between the gate electrode and the resistor electrode, and the isolation structure is closer to the resistor electrode than the gate electrode. The semiconductor device structure further includes a source/drain (S/D) region disposed in the semiconductor substrate and between the gate electrode and the isolation structure. The S/D region is electrically connected to the resistor electrode.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: November 22, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11508707
    Abstract: A semiconductor package including at least one functional die; at least one dummy die free of active circuit, wherein the dummy die comprises at least one metal-insulator-metal (MIM) capacitor; and a redistribution layer (RDL) structure interconnecting the MIM capacitor to the at least one functional die.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: November 22, 2022
    Assignee: MediaTek Inc.
    Inventors: Yao-Chun Su, Chih-Ching Chen, I-Hsuan Peng, Yi-Jou Lin
  • Patent number: 11508734
    Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: November 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Amirhasan Nourbakhsh, John K. Zahurak, Sanh D. Tang, Silvia Borsari, Hong Li
  • Patent number: 11508665
    Abstract: A method includes forming a plurality of dielectric layers, which processes include forming a first plurality of dielectric layers having first thicknesses, and forming a second plurality of dielectric layers having second thicknesses smaller than the first thicknesses. The first plurality of dielectric layers and the second plurality of dielectric layers are laid out alternatingly. The method further includes forming a plurality of redistribution lines connected to form a conductive path, which processes include forming a first plurality of redistribution lines, each being in one of the first plurality of dielectric layers, and forming a second plurality of redistribution lines, each being in one of the second plurality of dielectric layers.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Yuan Teng, Kuo Lung Pan, Yu-Chia Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chen-Hua Yu
  • Patent number: 11508658
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a semiconductor substrate having a first surface and a first optical coupler disposed on the first surface of the semiconductor substrate. The first optical coupler includes a first surface facing away from the first surface of the semiconductor substrate and a first lateral surface connected to the first surface of the first optical coupler. The first surface of the first optical coupler and the first lateral surface of the optical coupler define an angle greater than 90 degrees. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hau-Yan Lu, Felix Ying-Kit Tsui, Jing-Hwang Yang, Feng Yuan
  • Patent number: 11508662
    Abstract: A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: November 22, 2022
    Assignee: Intel Corporation
    Inventors: Robert Alan May, Wei-Lun Kane Jen, Jonathan L. Rosch, Islam A. Salama, Kristof Darmawikarta
  • Patent number: 11508604
    Abstract: The present disclosure provides a micro light emitting diode transfer device and a micro light emitting diode transfer method. The micro light emitting diode transfer device includes a holding member, a light source, and a liquid crystals light valve. The liquid crystals light valve is disposed on a transmission path of planar light and includes a plurality of sub light valves. The micro light emitting diodes of irradiated part can be separated from the transfer substrate and adhere to a target substrate, and thereby the micro light emitting diodes can be selectively transferred.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: November 22, 2022
    Inventor: Yong Fan
  • Patent number: 11508667
    Abstract: Some examples described herein provide for a shield in an integrated circuit (IC) structure for memory protection. In an example, an IC structure includes a semiconductor material, an interconnect structure, and a shield. The semiconductor material has a protected region. Devices are disposed in a first side of the semiconductor material in the protected region. The interconnect structure is disposed on the first side of the semiconductor material. The interconnect structure interconnects the devices in the protected region. The shield is disposed on a second side of the semiconductor material opposite from the first side of the semiconductor material. The shield is positioned aligned with the protected region.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: November 22, 2022
    Assignee: XILINX, INC.
    Inventors: James Karp, Yan Wang