Abstract: A wireless communication technique enables equalization, soft demapping and phase error estimation functions to be performed jointly based on multiple observations of a transmitted symbol in wireless communication systems employing receive diversity. Multiple observations of a symbol are obtained from multiple antenna paths in a wireless receiver. Equalization, soft demapping and phase error estimation functions can be integrated within shared hardware, rather than distributed among separate hardware blocks, promoting reduced size, complexity and cost in a wireless receiver.

Abstract: A high-speed modem operates at speeds as high as 64 kbps in both the downlink direction from a digital modem to an analog subscriber and at an increased speed in the uplink direction from the analog subscriber back to the digital modem. Known systems provide a 56 kbps connection in the downlink direction but only provide for as high as a 33.6 kbps connection in the uplink direction. The present invention centers on the development of apparatus, systems, and methods for remote-echo cancellation whereby signal processing in the modem endpoints is used to remotely cancel an echo component at the input to a network-interface's ADC. Heretofore, this echo component has limited the achievable uplink data rate. Hence the present invention enables symmetric 56 kbps modem connections using POTS lines or the POTS channel within a DSL when line conditions warrant.

Abstract: Differential unitary space-time (DUST) communication is a technique for communicating via one or more antennas by encoding the transmitted data differentially using unitary matrices at the transmitter, and decoding differentially without knowing the channel coefficients at the receiver. Since channel knowledge is not required at the receiver, DUST is ideal for use on wireless links where channel tracking is undesirable or infeasible. Disclosed are a class of Cayley codes for DUST communication that can produce sets of unitary matrices that work with any number of antennas, and has efficient encoding and decoding at any rate. The codes are named for their generation via the Cayley transform, which maps the highly nonlinear Stiefel manifold of unitary matrices to the linear space of skew-Hermitian matrices. The Cayley codes can be decoded using either successive nulling/cancelling or sphere decoding.

Abstract: In one aspect, apparatus and method are provided for communicating data in the form of transmission symbols conveyed in a carrier signal, wherein each transmission symbol is from a symbol set comprising a plurality of symbols which are collectively capable of representing any combination of values for at least three bits of data, wherein each symbol of the symbol set is defined with at most one transition of signal level in the carrier signal. In another aspect, apparatus and method are provided for communicating any combination of values for at least three data bits in the form of a respective transmission symbol conveyed in a carrier signal, wherein the transmission symbol is uniquely defined by a respective combination of a signal level transition, a lack of signal level transition, a signal region, and a cross-over between signal regions in the carrier signal.

Abstract: A filter and processing sequence is described that efficiently combines and performs two or more tasks required to demodulate a composite 3G (third generation) wireless signal formed by a combination of wideband 3.84 MHz (Universal Mobile Telecommunications System, identified, as acronym “UMTS”, or Universal Mobile Telecommunications System Terrestrial Radio Access, identified as acronym “UTRA”) carriers and narrowband 1.2288 MHz CDMA-2000 carriers. The three tasks, applied to each spectral component of the 3G wireless signal and described in the order of a traditional filtering structure are: Spectral translation, Bandwidth Reduction, and Sample Rate Selection. These tasks are traditionally implemented in three distinct pieces of hardware or software modules.

Abstract: The present invention includes a time-division-multiple-access (TDMA) communication system having a base station and at least one mobile station, each transmitting and receiving an analog radio-frequency signal carrying digitally coded speech. The speech is encoded using a vocoder which samples a voice signal at variable encoding rates. During periods when the radio-frequency channel is experiencing high levels of channel interference, the encoded voice channel having a lower encoding rate is chosen. This low-rate encoded voice is combined with the high degree of channel coding necessary to ensure reliable transmission. When the radio-frequency channel is experiencing low levels of channel interference, less channel coding is necessary and the vocoder having a higher encoding rate is used. The high-rate encoded voice is combined with the lower degree of channel coding necessary to ensure reliable transmission.

Abstract: A communication circuit (28) is designed with a signal processing circuit (370) arranged to produce a first plurality of data signals and receive a second plurality of data signals. A transmit circuit (364) is coupled to receive the first plurality of data signals and transmit each data signal of the first plurality of data signals on a respective transmit frequency in a predetermined sequence of transmit frequencies. A receive circuit (362) is coupled to receive each data signal of the second plurality of data signals from a remote transmitter on the respective transmit frequency in the predetermined sequence. The receive circuit applies the second plurality of data signals to the signal processing circuit.

Abstract: One aspect of the present invention is a method for combining a direct sequence spread spectrum signal comprising signal components that each may be characterized by a space variable and a time variable comprising the steps of: dispreading the signal components; and determining a set of combining coefficients from the signal components using a Minimum Mean Square Error combining method that considers the space and time variables of the signal components in parallel. The Minimum Mean Square Error combining methods may utilize iterative methods such as the Least Mean Squares method or the Recursive Least Squares method.

Abstract: In a tap 1 in a shift register of a waveform equalizer, data of an input signal is stored in a data storing FF 111. A tap coefficient computing unit 114 calculates a tap coefficient, which is stored in a tap coefficient storing FF 112 and output to an absolute value computing unit 115. The unit 115 obtains the absolute value of the tap coefficient. A comparator 116 compares the absolute value to a threshold value. A masking unit 117 masks and outputs the data from the data storing FF 111 to a multiplier 113 if the absolute value is smaller than the threshold value, while outputting the data from the data storing FF 111 without change if the absolute value is no less than the threshold value. The multiplier 113 multiplies the data of the input signal by the tap coefficient and outputs a signal to an adder 108.

Abstract: A method and apparatus for parallel decoding of turbo encoded data. The method includes multiple Soft In Soft Out (SISO) modules arranged in parallel such that each module supplies an input to one SISO and takes an input from another SISO data encoded for multiple parallel SISOs is received by a receiver and decoded in the abovementioned parallel configuration.

Abstract: Mask compliance of a digital signal from a reference device is determined. Bit error rates for first sampling points for a low mask region are detected. The bit error rates for the first sampling points are averaged to produce an average low mask region error rate. Bit error rates for second sampling points for a high mask region are detected. The bit error rates for the second sampling points are averaged to produce an average high mask region error rate.

Abstract: An XDSL system comprising a hybrid circuit in operative communication with a transmission line and an XDSL modem associated with a subscriber premises. The hybrid circuit comprises a plurality of selectable impedance circuits having different impedance values. A controller selectively engages each of the impedance circuits in-line with the XDSL modem and the transmission line. The controller records the performance of the modem with each circuit engaged, and selects the desired impedance circuit as a function of the performance characteristics associated with each of the impedance circuits. The impedance circuit which provides the best performance characteristic is selected as the impedance circuit for normal modem operation.

Abstract: A frequency shift key decoding apparatus, having a frequency divider, a signal frequency splitter, and a demodulator. The signal frequency splitter has a frequency synthesizer, (n?1) first mixers, n second mixers, and n filters, where n is an integer equal to or larger than 2. The present invention can be applied to a multi-function wireless receiver that supports multiple peripherals. Since a plurality of local carrier signals is generated by only (n?1) mixers, the frequency of the local carrier signals can be randomly changed. As the mixers occupy a very small area of the integrated circuit chip, the fabrication cost is low. Further, since the mixers are easily implemented using a digital circuit, the frequency shift key decoding apparatus, and even the whole wireless receiver can be implemented in a single chip.

Abstract: A receiver which suppresses inter-cluster multipath interference by processing an impulse channel response consisting of two multipath clusters, each cluster having groups of signals with multiple delays. In one embodiment, the receiver includes a single antenna and parallel-connected delay units used to align the groups of signals before being input into respective sliding window equalizers. The outputs of the equalizers are combined at chip level via a combiner which provides a single output. In another embodiment, a cluster multipath interference suppression (CMIS) circuit is incorporated into the receiver. The CMIS circuit includes a hard decision unit and a plurality of signal regeneration units to generate replicas of the multipath clusters. The replicas are subtracted from the respective outputs of the delay units and the results are input to the respective sliding window equalizers. In another embodiment, multiple antennas are used to receive and process the clusters.

Abstract: A digital filtering system for filtering sample data includes a delay network for delaying input sample data to provide multiple delayed sample data outputs. The filtering system also includes a filter network represented by a decomposed coefficient weighting matrix for processing the delayed sample data outputs. A processor produces a filtered output by computing a weighted product summation of the delayed sample data outputs and the coefficient weighting matrix. The decomposed coefficient weighting matrix is derived by factoring a first coefficient weighting matrix with a common row factor and/or sparse matrix or by factoring based on matrix row or column symmetry.

Abstract: A turbo decoder system (1) for decoding turbo coded bits, is provided with a system input (2) and a plurality of turbo decoders (3; 3-1, . . . 3-n) each having a turbo decoder input (4; 4-1, . . . 4-n). The plurality of turbo decoders (3; 3-1, . . . 3-n) is arranged in parallel, and the system (1) is further provided with an allocating device (6) coupled between the system input (2) and the turbo decoder inputs (4; 4-1, . . . 4-n) for dynamically allocating the turbo coded bits to one of the turbo decoders (3; 3-1, . . . 3n).

Abstract: A power saving operation control method and device for a phase comparator unit are provided.

Abstract: A receiver includes clock termination circuitry that is capable of applying either a terminating impedance or a high impedance to a transmission path that carries a clock signal. When multiple of these receivers are used to service data links that share a clock signal, one of the clock termination circuits applies the terminating impedance to the transmission path that carries the clock signal while the other clock termination circuit(s) applies a high impedance to the transmission path. The receiver also includes a plurality of high rate serial bit stream buffers and a clock signal buffer along with the clock termination circuitry. In other embodiments, the receiver includes a deserializer and may include a controller. The receiver may service a dual link Digital Visual Interface.

Abstract: A signal to noise ratio estimator and method for a received signal which includes a communication component and a noise component is disclosed. One embodiment is an in-service, blind, decision-directed estimator for a CPFSK communication signal. A preferred embodiment determines the power of a communication signal component by combining the received signal with a signal that is a delayed complex conjugate of the received signal and then removing the real component of the combined signal.

Abstract: The invention relates to a method of adjusting a radio frequency signal produced by radio frequency circuitry in response to receipt of phase and amplitude control signals from digital baseband circuitry which operates to convert digital data signals into such phase and amplitude control signals. The phase and amplitude control signals are adjusted in the digital baseband circuitry in order to compensate for time alignment errors which occur in the radio frequency circuitry.