Abstract: An adaptive smoother includes a phase lock loop, a scintillation amplitude estimator and a fixed delay smoother operating on amplitude estimates for providing improved phase and/or code delay estimates of coherently modulated signals in the presence of dynamic phase process and time varying amplitudes. The adaptive smoother can be applied to GPS communication signals that are subject to fading due to small-scale temporal and spatial variations in ionospheric electron density. The adaptive smoother in a communication or navigation receiver results in improved signal tracking and navigation solutions.

Abstract: There is provided a system for testing modem training of a first modem and a second modem. The system includes a line simulator interposed between the first and second modems, and a processor for (a) controlling the line simulator to simulate a line length, (b) controlling the first modem to train with the second modem, and (c) saving data related to the modem training.

Abstract: A quality factor is associated to each carrier within a multicarrier system wherein a loading constant is computed as the quotient of a difference and the number of carriers that have no bits allocated, the difference being the difference of the sum of the bit error rates for carriers that have no bits allocated and the total remaining number of data bits that are not allocated, and allocating a number of bits to a carrier that has no bits allocated, the number of bits being the difference of the quality factor and the loading constant rounded to nearest integer, repeating the allocation until a predetermined fraction of the carriers have bits allocated, and reiterating the above steps until all carriers have bits allocated.

Abstract: Methods and apparatus for performing synchronization and DC-offset compensation in FM transmission systems significantly reduce the overhead associated with transmitting a conventional digital preamble at the start of each of a succession of transmitted digital data packets. According to exemplary embodiments, a multi-part digital preamble includes a short, substantially DC-free leading part followed by a code-protected synchronization part which is not necessarily substantially DC-free. The leading part provides for coarse DC offset estimation and synchronization, while the coded synchronization part carries timing and/or other useful information which can be unique for each packet. One or more substantially DC-free trailing parts follow the synchronization part, or are included in the synchronization part itself, and provide for fine tuning of the DC-offset estimate.

Abstract: A signal processing system including at least one control loop having a forward path and a feedback path. A signal processor produces a representation of the desired downstream output amplitude and phase as a pair of substantially orthogonal signal components. A feedback-path splitter splits a feedback signal into a plurality of substantially orthogonal feedback signal components which are combined with the corresponding substantially orthogonal signal components to create error signals. A plurality of modulators control the amplitude, frequency, and/or phase of the pair of substantially orthogonal signal components on the basis of control signals which are derived from the error signals. The outputs of the plurality of modulating means are then combined into an output signal. A phase-shift controller in the forward path of the control loop derives the control signals from the error signals on the basis of monitored signal values from at least one predetermined point in the signal processing system.

Abstract: Methods of measuring phase angle and decoding a pseudo-random noise (PRN) code by applying High Resolution Correlators, having three or more correlators signals, where at least two signals, or multiples of two, are equally distanced advanced or delayed signals from the PRN signal with the option of one signal substantially in sync with the PRN signal. A phase tracking error is computed when measuring phase angle or adjusting the relative timing difference by adjusting the phase of the locally generated PRN signals when the error signal has a non-zero magnitude, in a manner to drive said error signal to zero when decoding the PRN code.

Abstract: A method for determining and reducing or eliminating mid-range and long-rang echoes in the digital data transmission (in ATSC VSB system) is described. A portion of an ATSC VSB television signal is separated from the rest of the signal, certain values are set to zero and it is correlated with a first vector of data. The result of the correlation represents a channel model as affected by echoes within the channel, and then a second vector of data is added to it to derive correction information useful in positioning moveable filter taps to suppress the most prominent echoes.

Abstract: Correlation times for a RAKE receiver are determined from time differentials between multipath components of a received signal based on correlation metrics, preferably signal strength measurements, associated with the multipath components. According to various embodiments of the present invention, selection strategies are employed in which “desired signal collecting” and “interference collecting” correlation times may be selected using average optimal (AO) or instantaneous optimal (IO) selection criteria. These criteria may include, for example, thresholds for signal strengths associated with multipath components of a signal at the correlation times, where the signal strengths may include absolute or relative measures of signal power or signal to noise ratio. According to alternative embodiments, correlation times are selected using an inverse filter of an estimated channel response. Related apparatus is also described.

Abstract: A common dual-mode physical layer architecture for a communications receiver is capable of receiving either frequency hopping spread spectrum signals or direct sequence spread spectrum signals. A delta-sigma modulator is configured as an oversampling A/D converter with predetermined quantization noise shaping characteristics. The respective spread spectrum signal is processed by the delta-sigma modulator and then filtered via a decimation filter such as a (sin(x))/x filter to generate a quadrature signal having sufficient resolution to meet industry standards.

Abstract: An apparatus comprising a first circuit, a second circuit and a logic circuit. The first circuit may be configured to generate a first output signal having a first data rate in response to an input signal having a second data rate and clock signal having the second data rate. The second circuit may be configured to generate a second output signal in response to the input signal and the clock signal. The logic circuit may be configured to generate a clock signal in response to the first output signal and the second output signal.

Abstract: For enabling a stable clock signal to be extracted from even an input signal of which the duty factor is made worse, there is presented a clock extraction circuit applicable to an optical signal receiver equipped in an apparatus for use in the optical data communication. The clock extraction circuit includes a rising edge differential circuit (12) for differentiating the input signal at the rising edge thereof, a first monostable multivibrator (13) for processing the output from the differential circuit (12), a second monostable multivibrator (14) for processing the output from the first monostable multivibrator (13), an OR gate (15) for carrying out the logical OR between the output signals from the first and second monostable multivibrators (13) and (14) and circuitry for variably varying output pulse width, which processes the result of the logical OR.

Abstract: A method for demodulating a received signal including a pilot signal while estimating the fading distortion of data by detecting the fading distortion of a unique word as the pilot signal inserted into multiple sections of the received signal, the method having the steps of: (1) setting part of data as an extended the unique word; (2) detecting the fading distortion of the unique word as the pilot signal as a first fading distortion and detecting the fading distortion of the extended unique word as a second fading distortion; (3) estimating the fading distortion of data based on the first and second fading distortions; and (4) demodulating data based on the fading distortion of data.

Abstract: A post-HPA filter rejection equalizer system and method locally equalizes post-HPA filtering. A predistorter (20) uses a phase error to control the predistortion, and an equalizer (46) uses a magnitude error to control the equalization. The equalizer samples the HPA output multiple occurrences in a burst fashion. The equalized signal is then used to determine phase and magnitude errors. The phase errors (54) are used to update the predistorter (20), and the magnitude errors (52) are used to update the analytic equalizer.

Abstract: A data clock generator, a data clock generating method and a storage medium therefor are provided, which make it possible to reduce burden on a PLL circuit and substantially reduce jitter in the generated data clock signal, as well as achieve a sufficiently wide lock range of the PLL circuit. Data packets are supplied, which include at least a plurality of data samples and time stamps which are smaller in number than the number of the plurality of data samples. Time samples are generated, respectively, for the data samples from the time stamps of the supplied data packets. A PLL circuit generates a data clock signal based on the time samples for the respective data samples.

Abstract: The invention relates to a method of estimating a transmission channel from a signal (S) received by that channel. The received signal corresponds to a transmitted training sequence, and the method includes the following steps: acquiring a statistic of the transmission channel, establishing an estimate (Xp) of the impulse response of the channel weighted by the statistic of the channel of the received signal (S).

Abstract: An iterative decoder with a gain controller in a mobile communication system. In the iterative decoder, a first component decoder receives a first extrinsic information signal, a first parity signal, and a systematic code signal, decodes the systematic code signal out of the received signals, and generates a primary decoded signal including a second extrinsic information component. Here, the first and second extrinsic information signals remove noise in the input signals to the first and second component decoders. A second component decoder receives the primary decoded signal from the first component decoder and a second parity signal, decodes the decoded signal out of the received signals, and generates a secondary decoded signal and the first extrinsic information signal. One or more gain controllers are connected between the first and second component decoders, for attenuating either or both the first and second extrinsic information signals.

Abstract: Embodiments of the present invention deal generally with circuitry and methods for converting a sampled digital signal (32) to a naturally sampled digital signal (34). One embodiment relating to a method includes receiving the sampled digital signal, calculating a duty ratio estimate (33) using feedback (52), and using interpolation (62) to determine the naturally sampled digital signal. Circuitry for converting a sampled digital signal (32) to a naturally sampled digital signal (34) includes a natural sampler, where the natural sampler includes an input to receive the sampled digital signal (32) and an input to receive a feedback signal (52). The natural sampler has an output to provide the naturally sampled digital signal (34). In one embodiment, the natural sampler calculates a duty ratio (33) using the feedback signal (52) and uses interpolation to determine the naturally sampled digital signal (34).

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate (i) a first control signal, (ii) a second control signal, (iii) one or more first clock signals and (iv) a first data signal operating at a first speed in response to (i) an input data signal and (ii) a reference clock signal. The second circuit may be configured to generate one or more intermediate data signals operating at a second speed in response to (i) the first control signal, (ii) the one or more first clock signals and (iii) the first data signal. The third circuit may be configured to generate an output data signal operating at a third speed in response to (i) the second control signal and (ii) the one or more intermediate data signals.

Abstract: Carrier recovery control circuitry incorporates a dual-phase accumulator architecture to facilitate carrier recovery in spread spectrum communications. The associated receiver is configured to downconvert and despread the spread spectrum signal to a baseband signal. Demodulation circuitry operating on the baseband signals provides an error signal representing the difference between the sampled signal and the ideal symbol. This error signal, through a loop filter, is to provided to a first phase accumulator running at the symbol rate. The first phase accumulator accumulates a first phase correction adjustment for each symbol duration. A second phase accumulator running at the sampling rate is set by the output of the first phase accumulator to cause the second phase accumulator to accumulate an additional phase correction adjustment that is dependent upon the first phase correction adjustment and the sample rate.

Abstract: An AGC circuit is capable of prevention of occurrence of distortion of an input signal of an A/D converter and enables use of full scale of the A/D converter even in demodulation of a signal of a modulation system, in which a frequency axis is commonly occupied by a plurality of receivers, such as CDMA. The AGC circuit includes an amplifier to amplify an input signal and a controller to compare an amplitude of the input signal and a first reference value and control a gain of the amplifier depending upon a result of the comparison. The AGC circuit further includes first reference value controller to detect a maximum value of the amplitude of the input signal amplified by the amplifier and controlling the first reference value depending upon the maximum value.