Abstract: Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant.

Abstract: A method of manufacturing a semiconductor device, comprising, forming a first gate electrode in a first region of a semiconductor substrate and forming a second gate electrode in a second region of the semiconductor substrate, forming a first sidewall along a lateral wall of the first gate electrode and forming a second sidewall along a lateral wall of the second gate electrode, forming an oxide film to cover the semiconductor substrate, the first gate electrode, the second gate electrode, the first sidewall and the second sidewall, forming a resist above the oxide film to cover the first region, removing the oxide film in the second region by etching the oxide film with the resist serving as a mask, removing the resist, and executing a plasma process by using a gas containing chlorine with respect to the semiconductor substrate and the oxide film in the first region.

Abstract: A memory device comprising a plurality of tunnel junctions (TJs) includes a bottom wiring layer; a top wiring layer; a plurality of TJs contacting the bottom wiring layer and the top wiring layer; and a plurality of tunnel junction vias (TJVs) contacting the bottom wiring layer and the top wiring layer, wherein the plurality of TJVs each have a lower resistance the each of the plurality of TJs, wherein the plurality of TJVs comprise at least one concave surface, and wherein the at least one concave surface of the plurality of TJVs is configured to trap etched material during formation of the TJVs so as to reduce the resistance of the plurality of TJVs.

Abstract: The invention relates to a process for the production of electrolyte capacitors having a low equivalent series resistance and low residual current for high nominal voltages, electrolyte capacitors produced by this process and the use of such electrolyte capacitors.

Abstract: A method for fabricating a semiconductor device includes: forming a thin film over trenches by using a first source gas and a first reaction gas; performing a first post-treatment on the thin film by using a second reaction gas; and performing a second post-treatment on the thin film by using a second source gas.

Abstract: An organic semiconducting composition consists essentially of an N,N-dicycloalkyl-substituted naphthalene diimide and a polymer additive comprising an insulating or semiconducting polymer having a permittivity at 1000 Hz of at least 1.5 and up to and including 5. This composition can be used to provide a semiconducting layer in a thin-film transistor that can be incorporated into a variety of electronic devices.

Abstract: A semiconductor device has a substrate with an inductor formed on its surface. First and second contact pads are formed on the substrate. A passivation layer is formed over the substrate and first and second contact pads. A protective layer is formed over the passivation layer. The protective layer is removed over the first contact pad, but not from the second contact pad. A conductive layer is formed over the first contact pad. The conductive layer is coiled on the surface of the substrate to produce inductive properties. The formation of the conductive layer involves use of a wet etchant. The second contact pad is protected from the wet etchant by the protective layer. The protective layer is removed from the second contact pad after forming the conductive layer over the first contact pad. An external connection is formed on the second contact pad.

Abstract: An apparatus comprising a microelectromechanical system. The microelectromechanical system includes a crystalline structural element having dislocations therein. For at least about 60 percent of adjacent pairs of the dislocations, direction vectors of the dislocations form acute angles of less than about 45 degrees.

Abstract: The invention relates to improvements in the polishing of a layer of germanium by a method which includes a first step of chemical-mechanical polishing of the surface of the germanium layer that is carried out with a first polishing solution having an acidic pH. The first polishing step is then followed by a second step of chemical-mechanical polishing of the surface of the germanium layer carried out with a second polishing solution having an alkaline pH. The polished heteroepitaxial germanium layer has a surface microroughness of less than 0.1 nm RMS and a surface macroroughness corresponding to a surface haze level of less than 0.5 ppm.

Abstract: A method for fabricating a conductive contact is provided, including: providing a semiconductor substrate with a dielectric layer formed thereover and two conductive regions and an isolation element formed therein, wherein the isolation element isolates the two conductive regions from each other; forming an opening in the dielectric layer, exposing a top surface of the isolation element and a portion of a top surface of each of the conductive regions; performing an epitaxy process and forming a conductive semiconductor layer within the opening, overlying the top surface of the isolation element and the portion of the top surface of each of the conductive regions; and forming a conductive layer in the opening, overlying the conductive semiconductor layer and filling the opening.

Abstract: By combining an anneal process for adjusting the effective channel length and a substantially diffusion-free anneal process performed after a deep drain and source implantation, the vertical extension of the drain and source region may be increased substantially without affecting the previously adjusted channel length. In this manner, in SOI devices, the drain and source regions may extend down to the buried insulating layer, thereby reducing the parasitic capacitance, while the degree of dopant activation and thus series resistance in the extension regions may be improved. Furthermore, less critical process parameters during the anneal process for adjusting the channel length may provide the potential for reducing the lateral dimensions of the transistor devices.

Abstract: In a further embodiment of the present invention, a method for preparing a contact structure includes the steps of forming a conductive stack on the semiconductor substrate; forming a patterned mask on the conductive stack; forming a depression in an upper portion of the conductive stack; forming a spacer layer on the surface of the depression and the patterned mask; forming a mask block filling the depression; removing a portion of the spacer layer not covered by the mask block; and removing a portion of the conductive stack by using the mask block and the patterned mask to form the contact structure including at least one tall contact plug under the patterned mask and at least one the short contact plug under the mask block.

Abstract: A method of forming large microchannels in an integrated circuit by etching an enclosed trench into the substrate and later thinning the backside to expose the bottom of the trenches and to remove the material enclosed by the trench to form the large microchannels. A method of simultaneously forming large and small microchannels. A method of forming structures on the backside of the substrate around a microchannel to mate with another device.

Abstract: Methods of forming substrates having two-sided microstructures therein include selectively etching a first surface of the substrate to define a plurality of alignment keys therein that extend through the substrate to a second surface thereof. A direct photolithographic alignment step is then performed on a second surface of the substrate by aligning a photolithography mask to the plurality of alignment keys at the second surface. This direct alignment step is performed during steps to photolithographically define patterns in the second surface.

Abstract: The present invention provides methods of selectively depositing refractory metal and metal nitride cap layers onto copper lines inlaid in a dielectric layer. The methods result in formation of a cap layer on the copper lines without significant formation on the surrounding dielectric material. The methods typically involve exposing the copper lines to a nitrogen-containing organo-metallic precursor and a reducing agent under conditions that the metal or metal nitride layer is selectively deposited. In a particular embodiment, an amino-containing tungsten precursor is used to deposit a tungsten nitride layer. Deposition methods such as CVD or ALD may be used.

Abstract: A method of forming an integrated circuit structure includes forming a bottom electrode layer over a substrate; forming magnetic tunnel junction (MTJ) layers over the bottom electrode layer; patterning the MTJ layers to form a MTJ stack; forming a dielectric layer covering the MTJ stack; forming an opening in the dielectric layer to expose a portion of the MTJ stack; filling the opening with a top electrode material; and performing a planarization to the top electrode material. After the step of performing the planarization, the top electrode material and the dielectric layer are patterned, wherein a first portion of the top electrode material in the opening forms a top electrode, and a second portion of the top electrode material forms a metal strip over the dielectric layer and connected to the top electrode.

Abstract: To achieve enlargement and high definition of a display portion, a single crystal semiconductor film is used as a transistor in a pixel, and the following steps are included: bonding a plurality of single crystal semiconductor substrates to a base substrate; separating part of the plurality of single crystal semiconductor substrates to form a plurality of regions each comprising a single crystal semiconductor film over the base substrate; forming a plurality of transistors each comprising the single crystal semiconductor film as a channel formation region; and forming a plurality of pixel electrodes over the region provided with the single crystal semiconductor film and a region not provided with the single crystal semiconductor film. Some of the transistors electrically connecting to the pixel electrodes formed over the region not provided with the single crystal semiconductor film are formed in the region provided with the single crystal semiconductor film.

Abstract: A method of forming a semiconductor structure includes providing a substrate including a fin at a surface of the substrate, and forming a fin field-effect transistor (FinFET), which further includes forming a gate stack on the fin; forming a thin spacer on a sidewall of the gate stack; and epitaxially growing a epitaxy region starting from the fin. After the step of epitaxially growing the epitaxy region, a main spacer is formed on an outer edge of the thin spacer. After the step of forming the main spacer, a deep source/drain implantation is performed to form a deep source/drain region for the FinFET.

Abstract: Methods for fabricating control gates in non-volatile storage are disclosed. When forming stacks for floating gate memory cells and transistor control gates, a sacrificial material may be formed at the top of the stacks. After insulation is formed between the stacks, the sacrificial material may be removed to reveal openings. In some embodiments, cutouts are then formed in regions in which control gates of transistors are to be formed. Metal is then formed in the openings, which may include the cutout regions. Therefore, floating gate memory cells having at least partially metal control gates and transistors having at least partially metal control gates may be formed in the same process. A barrier layer may be formed prior to depositing the metal in order to prevent silicidation of polysilicon in the control gates.

Abstract: In a modern 0.15 ?m power MOSFET, aluminum voids (voids formed in an aluminum-type electrode) are generated frequently in trench portions (source contact trenches) caused by the reduction of a cell pitch for refinement. It is considered to be attributable to the defects which are generated mainly due to a sudden increase of the aspect ratio from 0.84 in the previous generation to 2.8 in the current generation. Accordingly, concave portions of repetitive trenches having a high aspect ratio are filled with an aluminum-type metal by ionized sputtering throughout the processing, from the formation to the filling of an aluminum-type metal seed film.