Abstract: A substrate is diced using a program-controlled pulsed laser beam apparatus having an associated memory for storing a laser cutting strategy file. The file contains selected combinations of pulse rate Deltat, pulse energy density E and pulse spatial overlap to machine a single layer or different types of material in different layers of the substrate while restricting damage to the layers and maximising machining rate to produce die having predetermined die strength and yield. The file also contains data relating to the number of scans necessary using a selected combination to cut through a corresponding layer. The substrate is diced using the selected combinations. Gas handling equipment for inert or active gas may be provided for preventing or inducing chemical reactions at the substrate prior to, during or after dicing.

Abstract: An integrated circuit includes at least one photodiode of the floating substrate type which is associated with a read transistor. The photodiode is formed from a buried layer lying beneath the floating substrate and an upper layer lying on the floating substrate. The upper layer incorporates the source and drain regions of the read transistor. The source and drain regions are produced on either side of the gate of the read transistor. An isolating trench is located alongside the source region and extends from the upper surface of the upper layer down to below the buried layer, so as to isolate the source region from said buried layer.

Abstract: A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers.

Abstract: An electronic device includes an electronic element having a detecting part on one surface thereof, a base member, bumps, and an adhesive film. The base member is arranged to face the one surface of the electric element. The bumps are arranged between the electric element and the base member for electrically coupling the electric element and the base member. The adhesive film is attached to the one surface of the electronic element and has an electronic insulating property. In addition, the adhesive film has a hollow part at a portion corresponding to the detecting part in a manner separated from the detecting part. Furthermore, a first pressure in the hollow part is higher than a second pressure outside the hollow part.

Abstract: A solid electrolyte memory element comprising an inert cathode electrode, a reactive anode electrode and a solid electrolyte layer disposed between the inert cathode electrode and the reactive anode electrode, wherein the solid electrolyte layer comprises a solid electrolyte matrix having defect sites.

Abstract: A light emitting apparatus includes a substrate, a first metal layer, an insulating layer and at least one light emitting device. The first metal layer is disposed on the substrate. The insulating layer is disposed on the first metal layer. The light emitting device is disposed on the insulating layer.

Abstract: A semiconductor device such as a COF or the like is provided on a semiconductor chip on a film-like shaped flexile wiring substrate on which a wiring pattern is formed. Between the semiconductor chip and the flexile wiring substrate, a sealing resin is filled for protecting the semiconductor chip. In the semiconductor device, a resin trace is 0.1 to 1.0 mm in width and 10 ?m in thickness, the resin trace being formed when applying the sealing resin along a longitudinal side of the semiconductor chip.

Abstract: An integrated circuit can have a first substrate supporting a magnetic field sensing element and a second substrate supporting another magnetic field sensing element. The first and second substrates can be arranged in a variety of configurations. Another integrated circuit can have a first magnetic field sensing element and second different magnetic field sensing element disposed on surfaces thereof.

Abstract: A semiconductor device including a capacitor which includes a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode, the dielectric layer including: a first paraelectric film formed of a material containing a first metal element and at least one kind of second metal element; a second paraelectric film disposed between the first electrode and the first paraelectric film; and a third paraelectric film disposed between the second electrode and the first paraelectric film, wherein the second paraelectric film is formed of a material containing the first metal element but substantially not containing the second metal element, and the third paraelectric film is formed of a material containing the first metal element but substantially not containing the second metal element.

Abstract: A semiconductor device includes a circuit board which has a first main surface having first connection pads, a second main surface having second connection pads, a first opening passing through a vicinity of the first connection pads, and a second opening passing through a vicinity of the second connection pads. A first semiconductor element is mounted in a face-down state on the first main surface of the circuit board. First electrode pads are exposed into the second opening and connected to the second connection pads through the second opening. A second semiconductor element is mounted in a face-up state on the second main surface of the circuit board. Second electrode pads are exposed into the first opening and connected to the first connection pads through the first opening.

Abstract: In a nitride semiconductor light-emitting device having an active layer between an n-type nitride semiconductor layer and a p-type nitride semiconductor layer, the active layer has a multiple quantum well structure including a plurality of InxGa1-xN (0<x?1) quantum well layers and a plurality of InyGa1-yN (0?y<1) barrier layers stacked alternately, and at least one of the plurality of barrier layers has a super-lattice structure in which a plurality of barrier sub-layers having mutually different In composition ratios are stacked periodically.

Abstract: A LSI package encompasses: an interposer having board-connecting joints, which facilitate connection with a printed wiring board, and module-connecting terminals, part of the module-connecting terminals are assigned as interposer-site monitoring terminals; a signal processing LSI mounted on the interposer; and an I/F module having a plurality of interposer-connecting terminals, which are arranged to correspond to arrangement of the module-connecting terminals, and a transmission line to establish an external interconnection of signal, which is transmitted from the signal processing LSI, part of the interposer-connecting terminals are assigned as module-site monitoring terminals. The interposer-site and module-site monitoring terminals are configured to flow a monitoring current to confirm electric contact between the signal processing LSI and the I/F module.

Abstract: A semiconductor interconnection comprises a semiconductor device, a substrate adjacent the semiconductor device, and a plurality of spring contacts on the semiconductor device or the substrate. A plurality of solder connections are on the opposite semiconductor device or substrate. Each spring contact comprises a contact surface and a conductive material on the contact surface. Upon assembly of the semiconductor device and the substrate, the conductive material on the plurality of spring contacts makes contact with each of the plurality of solder connections. The conductive material is in a liquid state at manufacturing or operating temperatures of the semiconductor device. Thus, the conductive material could be a solid at room temperature and transition to a liquid state at the semiconductor's manufacturing or operating temperatures.

Abstract: A copper interconnection structure includes an insulating layer, an interconnection and a barrier layer. The insulating layer includes silicon (element symbol: Si), carbon (element symbol: C), hydrogen (element symbol: H) and oxygen (element symbol: O). The interconnection is located on the insulating layer, and the interconnection includes copper (element symbol: Cu). The barrier layer is located between the insulating layer and the interconnection. The barrier layer includes an additional element, carbon (element symbol: C) and hydrogen (element symbol: H). The barrier layer has atomic concentrations of carbon (element symbol: C) and hydrogen (element symbol: H) maximized in a region of a thickness of the barrier layer where the atomic concentration of the additional element is maximized.

Abstract: Systems for cooling the backside of a semiconductor die located in a die-down integrated circuit (IC) package are described. The IC package is attached to the topside of a printed circuit board (PCB) with the backside of the die residing below the topside surface of the PCB. A cooling plate is attached to the backside of the die and thermally connected to a heat sink located above the topside surface of the PCB via conduits that pass through openings in the PCB.

Abstract: A basic building block for wafer scale stacked integrated circuits is disclosed. The building block includes an integrated circuit device having an integrated circuit substrate having a circuit layer sandwiched between a buffer layer and a dielectric layer. The dielectric layer has a top side and a bottom side, the bottom side being in contact with the circuit layer. The top surface of the dielectric layer includes a plurality of pads. Each pad extends above the top surface by a predetermined distance. The pads have dimensions that reduce irregularities in the top surface of the pads. In addition, the pads are arranged in a manner to promote planarization of the surface of the wafer via CMP.

Abstract: A circuit device includes a semiconductor substrate on which a circuit element is formed, an electrode formed on a surface of the semiconductor substrate, an insulating layer formed on the electrode, a second wiring layer formed on the insulating layer, and a conductive bump which penetrates the insulating layer and electrically connects the electrode and the second wiring layer. The conductive bump is such that the size of crystal grains in a direction parallel with the surface of the semiconductor substrate is larger than the size of crystal grains in a conduction direction of the electrode and the wiring layer.

Abstract: An LED package is provided. The LED package comprises a metal plate, circuit patterns, and an LED. The metal plate comprises grooves. The insulating layer is formed on the metal plate. The circuit patterns are formed on the insulating layer. The LED is electrically connected with the circuit pattern on the insulating layer.

Abstract: The present invention is related to a ferroelectric storage medium for ultrahigh density data storage device and a method for fabricating the same. A supercell having high anisotropy is formed by controlling crystal structure and symmetry of unit structure (supercell) of artificial lattice by using an ordered alignment of predetermined ions having orientation of (perpendicular) deposition direction. Unit atomic layers of oxides having different polarization characteristic are deposited so that the supercell itself shows electric polarization having only two, upward and downward directions as one block of supercell having single-directional polarization. Oxide artificial lattices can be formed so as to have solely 180 degree domain structure, thus a single electric domain having improved anisotropic characteristic can be formed, thereby allowing capability of ultrahigh density data storage and long term data retention.

Abstract: One embodiment of the present invention is a thin film transistor, including: an insulating substrate; a gate electrode, a gate insulating layer and a semiconductor layer including an oxide, these three elements being formed over the insulating substrate in this order, and the gate insulating layer including: a lower gate insulating layer, the lower gate insulating layer being in contact with the insulating substrate and being an oxide including any one of the elements In, Zn or Ga; and an upper gate insulating layer provided on the lower gate insulating layer, the upper gate insulating layer comprising at least one layer; and a source electrode and a drain electrode formed on the semiconductor layer.