Patents Examined by Leslie Pilar Cruz
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Patent number: 10020287Abstract: Pass-through interconnect structures for microelectronic dies and associated systems and methods are disclosed herein. In one embodiment, a microelectronic die assembly includes a support substrate, a first microelectronic die positioned at least partially over the support substrate, and a second microelectronic die positioned at least partially over the first die. The first die includes a semiconductor substrate, a conductive trace extending over a portion of the semiconductor substrate, a substrate pad between the trace and the portion of the semiconductor substrate, and a through-silicon via (TSV) extending through the trace, the substrate pad, and the portion of the semiconductor substrate. The second die is electrically coupled to the support substrate via a conductive path that includes the TSV.Type: GrantFiled: December 4, 2015Date of Patent: July 10, 2018Assignee: Micron Technology, Inc.Inventors: David S. Pratt, Kyle K. Kirby, Dewali Ray
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Patent number: 10008598Abstract: In an embodiment, this invention discloses a top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate. The TD-LDMOS includes a source electrode disposed on a bottom surface of the semiconductor substrate. The TD-LDMOS further includes a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate. The TD-LDMOS further includes at least a trench filled with a conductive material and extending vertically from the body region near the top surface downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate.Type: GrantFiled: September 12, 2015Date of Patent: June 26, 2018Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Shekar Mallikarjunaswamy, John Chen, Yongzhong Hu
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Patent number: 9989824Abstract: The present application discloses an array substrate comprising a base substrate, a row of a plurality of pixel units, and a first gate line and a first common electrode line adjacent to the row of the plurality of pixel units and on a first side of the row of the plurality of pixel units in plan view of the array substrate. The first gate line and the first common electrode line are spaced apart by a gap; and a light shield at least partially covering the gap for reducing light leakage from the gap.Type: GrantFiled: December 10, 2015Date of Patent: June 5, 2018Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Xue Cao, Xi Chen, Dong Chen, Hailin Xue, Jianyun Xie, Jian Wang, Yanchen Li, Wei Zhao
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Patent number: 9985018Abstract: A high TCR tungsten resistor on a reverse biased Schottky diode. A high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A high TCR tungsten resistor embedded in a intermetal dielectric layer above a lower interconnect layer and below an upper interconnect layer. A method of forming a high TCR tungsten resistor on a reverse biased Schottky diode. A method of forming high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A method of forming high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A method of forming high TCR tungsten resistor embedded in a inter metal dielectric layer above a lower interconnect layer and below an upper interconnect layer.Type: GrantFiled: September 24, 2015Date of Patent: May 29, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Russell Carlton McMullan, Binu Kamblath Pushkarakshan, Subramanian J. Narayan, Swaminathan Sankaran, Keith Edmund Kunz
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Patent number: 9960153Abstract: The manufacturing yield of a semiconductor device is improved. There is provided a semiconductor device of a cascode coupling system, which is equipped with a plurality of normally-on junction FETs using as a material, a substance larger in bandgap than silicon, and a normally-off MOSFET using silicon as a material. At this time, the semiconductor chip has a plurality of junction FET semiconductor chips (semiconductor chip CHP0 and semiconductor chip CHP1) formed with the junction FETs in a divided fashion, and a MOSFET semiconductor chip (semiconductor chip CHP2) formed with the MOSFET.Type: GrantFiled: June 8, 2015Date of Patent: May 1, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Satoru Akiyama, Hiroyoshi Kobayashi, Hisao Inomata, Sei Saitou
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Patent number: 9941322Abstract: A semiconductor unit includes: a first device substrate including a first semiconductor substrate and a first wiring layer, in which the first wiring layer is provided on one surface side of the first semiconductor substrate; a second device substrate including a second semiconductor substrate and a second wiring layer, in which the second device substrate is bonded to the first device substrate, and the second wiring layer is provided on one surface side of the second semiconductor substrate; a through-electrode penetrating the first device substrate and a part or all of the second device substrate, and electrically connecting the first wiring layer and the second wiring layer to each other; and an insulating layer provided in opposition to the through-electrode, and penetrating one of the first semiconductor substrate and the second semiconductor substrate.Type: GrantFiled: October 22, 2015Date of Patent: April 10, 2018Assignee: SONY CORPORATIONInventors: Satoru Wakiyama, Hiroshi Ozaki
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Patent number: 9917090Abstract: Semiconductor devices and methods are provided in which vertical antifuse devices are integrally formed with vertical FET devices, wherein the vertical antifuse devices are formed as part of a process flow for fabricating the vertical FET devices. For example, a semiconductor device comprises a lower source/drain region formed on a substrate, and first and second vertical semiconductor fins formed on the lower source/drain region. First and second metal gate electrodes are formed on sidewalls of the first and second vertical semiconductor fins, respectively. An upper source/drain region is formed on an upper surface of the first vertical semiconductor fin, and a vertical source/drain contact is formed in contact with the upper source/drain region formed on the first vertical semiconductor fin. An upper end of the second vertical semiconductor fin is encapsulated in an insulating material so that the upper end of the second vertical semiconductor fin is floating.Type: GrantFiled: August 22, 2016Date of Patent: March 13, 2018Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
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Patent number: 9917078Abstract: The manufacturing yield of a semiconductor device is improved. There is provided a semiconductor device of a cascode coupling system, which is equipped with a plurality of normally-on junction FETs using as a material, a substance larger in bandgap than silicon, and a normally-off MOSFET using silicon as a material. At this time, the semiconductor chip has a plurality of junction FET semiconductor chips (semiconductor chip CHP0 and semiconductor chip CHP1) formed with the junction FETs in a divided fashion, and a MOSFET semiconductor chip (semiconductor chip CHP2) formed with the MOSFET.Type: GrantFiled: June 8, 2015Date of Patent: March 13, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Satoru Akiyama, Hiroyoshi Kobayashi, Hisao Inomata, Sei Saitou
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Patent number: 9905613Abstract: An electronic device includes a transistor. The transistor includes a body including a metal oxide; a gate electrode; and a gate insulating layer interposed between the body and the gate electrode, wherein the transistor is turned on or turned off by movement of oxygen vacancies in the body according to voltages applied to the gate electrode and the body.Type: GrantFiled: November 21, 2016Date of Patent: February 27, 2018Assignee: SK HYNIX INC.Inventor: Tae-Jung Ha
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Patent number: 9905475Abstract: A method includes isolating a first and at least a second region on a semiconductor substrate, and forming one or more devices on each of the first and at least second regions. Forming the one or more devices includes forming at least one gate structures in each of the first and at least second regions on a first surface of the substrate, depositing a spacer over the gate structures in each of the first and the at least second regions and over the first surface of the substrate, etching horizontal portions of the spacer in the first region, growing epitaxial portions in the first region in alignment with said at least one gate structure in the first region, oxidizing exposed surfaces of the epitaxial portions in the first region, and repeating the etching, growing and oxidizing steps for the at least second region.Type: GrantFiled: June 9, 2015Date of Patent: February 27, 2018Assignee: International Business Machines CorporationInventor: Effendi Leobandung
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Patent number: 9899566Abstract: The invention relates to an optoelectronic device comprising microwires or nanowires, each having at least one active portion (34, 39) between two insulated portions (32, 36, 40), the active portion having inclined flanks or having a diameter different from the diameter of at least one of the two insulated portions.Type: GrantFiled: December 27, 2013Date of Patent: February 20, 2018Assignee: ALEDIAInventor: BenoƮt Amstatt
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Patent number: 9899329Abstract: An electronic component array includes a backplane substrate, and a plurality of integrated circuit elements on the backplane substrate. Each of the integrated circuit elements includes a chiplet substrate having a connection pad and a conductor element on a surface thereof. The connection pad and the conductor element are electrically separated by an insulating layer that exposes at least a portion of the connection pad. At least one of the integrated circuit elements is misaligned on the backplane substrate relative to a desired position thereon. A plurality of conductive wires are provided on the backplane substrate including the integrated circuit elements thereon, and the connection pad of each of the integrated circuit elements is electrically connected to a respective one of the conductive wires notwithstanding the misalignment of the at least one of the integrated circuit elements. Related fabrication methods are also discussed.Type: GrantFiled: November 22, 2011Date of Patent: February 20, 2018Assignee: X-Celeprint LimitedInventor: Christopher Bower
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Patent number: 9893072Abstract: One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions. The nanofin transistor also has a surrounding gate insulator around the nanofin structure and a surrounding gate surrounding the channel region and separated from the nanofin channel by the surrounding gate insulator. The memory includes a data-bit line connected to the first source/drain region, at least one word line connected to the surrounding gate of the nanofin transistor, and a stacked capacitor above the nanofin transistor and connected between the second source/drain region and a reference potential. Other aspects are provided herein.Type: GrantFiled: July 20, 2015Date of Patent: February 13, 2018Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 9882152Abstract: A flexible display panel and a manufacturing method which is capable of removing a non-display area without damaging a display element layer, the flexible display panel includes a flexible substrate which includes a display area and a peripheral area outside of the display area, a display element layer disposed on the flexible substrate, and a neutral plane balancing layer disposed on the display element layer in the peripheral area, wherein the peripheral area of the flexible substrate in which the neutral plane balancing layer is disposed is folded towards a rear side of the display area along a first bending line, and the neutral plane balancing layer overlaps the first bending line.Type: GrantFiled: April 18, 2014Date of Patent: January 30, 2018Assignee: Samsung Display Co., Ltd.Inventors: Jun Namkung, Soon Ryong Park, Chul Woo Jeong
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Patent number: 9876102Abstract: A semiconductor device includes a layered structure forming multiple carrier channels including at least one n-type channel formed in a first layer made of a first material and at least one p-type channel formed in a second layer made of a second material and a set of electrodes for providing and controlling carrier charge in the carrier channels. The first material is different than the second material, and the first and the second materials are selected such that the n-type channel and the p-type channel have comparable switching frequency and current capability.Type: GrantFiled: September 2, 2015Date of Patent: January 23, 2018Assignee: Mitsubishi Electric Research Laboratories, Inc.Inventors: Koon Hoo Teo, Yuhao Zhang
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Patent number: 9852954Abstract: One illustrative method disclosed herein includes performing a first plurality of epitaxial deposition processes to form a first plurality of semiconductor materials selectively above the N-active region while masking the P-active region, performing a second plurality of epitaxial deposition processes to form a second plurality of semiconductor materials selectively above the P-active region while masking the N-active region, forming an N-type transistor in and above the N-active region and forming a P-type transistor in and above the P-active region.Type: GrantFiled: October 14, 2015Date of Patent: December 26, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Vara G. Reddy Vakada, Laegu Kang, Michael Ganz, Yi Qi, Puneet Khanna, Srikanth Balaji Samavedam, Sri Charan Vemula, Manfred Eller
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Patent number: 9842803Abstract: Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable layer on the conductive patterns. Methods of fabricating semiconductor devices are also provided.Type: GrantFiled: December 12, 2016Date of Patent: December 12, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jongmin Baek, Sangho Rha, Sanghoon Ahn, Wookyung You, Naein Lee
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Patent number: 9837313Abstract: Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line pattern that crosses word lines. Planarization can create parallelogram-shaped blocks of material that can overlie active areas to form sacrificial plugs, which can be replaced with conductive material to form contacts.Type: GrantFiled: May 10, 2016Date of Patent: December 5, 2017Assignee: Micron Technology, Inc.Inventors: Byron Neville Burgess, John K. Zahurak
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Patent number: 9828244Abstract: A compliant electrostatic transfer head and method of forming a compliant electrostatic transfer head are described. In an embodiment, a compliant electrostatic transfer head includes a base substrate, a cavity template layer on the base substrate, a first confinement layer between the base substrate and the cavity template layer, and a patterned device layer on the cavity template layer. The patterned device layer includes an electrode that is deflectable toward a cavity in the cavity template layer. In an embodiment, a second confinement layer is between the cavity template layer and the patterned device layer.Type: GrantFiled: September 30, 2014Date of Patent: November 28, 2017Assignee: APPLE INC.Inventors: Dariusz Golda, Stephen P. Bathurst, John A. Higginson, Andreas Bibl, Jeffrey Birkmeyer
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Patent number: 9793276Abstract: A semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limitation on the number of times of writing. In the semiconductor device, a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is provided in matrix and a wiring (also called a bit line) for connecting one memory cell to another memory cell and a source or drain electrode of the first transistor are electrically connected to each other through a source or drain electrode of the second transistor. Accordingly, the number of wirings can be smaller than that in the case where the source or drain electrode of the first transistor and the source or drain electrode of the second transistor are connected to different wirings. Thus, the degree of integration of the semiconductor device can be increased.Type: GrantFiled: November 9, 2015Date of Patent: October 17, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kiyoshi Kato, Shuhei Nagatsuka, Hiroki Inoue, Takanori Matsuzaki