Patents Examined by Lincoln D. Donovan
  • Patent number: 10840903
    Abstract: A semiconductor module according to embodiments includes a first external terminal, a second external terminal, a first semiconductor switch which is electrically connected between the first external terminal and the second external terminal and includes a first gate electrode, a second semiconductor switch which is electrically connected in parallel with the first semiconductor switch, between the first external terminal and the second external terminal, and includes a second gate electrode, a first fuse electrically connected between the first external terminal and the first semiconductor switch, and a second fuse electrically connected between the second external terminal and the first semiconductor switch.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: November 17, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Hiratsuka, Nobuto Fujiwara
  • Patent number: 10840744
    Abstract: An inductive power transmitter comprising: at least one power transmitting coil configured to generate an inductive power transfer (IPT) field; and an object detection system configured to detect objects in or adjacent a space occupied by the IPT field when generated; wherein the object detection system is configured to detect a receiver object based on a tag associated with the receiver object.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: November 17, 2020
    Assignee: Apple Inc.
    Inventor: Ali Abdolkhani
  • Patent number: 10840913
    Abstract: Circuits, apparatuses, and methods are disclosed for frequency division. In one such example circuit, a frequency divider is configured to alternate between providing a common frequency clock signal as an output clock signal through a first circuit responsive to a reference clock signal and providing a reduced frequency clock signal as the output clock signal through a second circuit responsive to the reference clock signal. The first and second circuits share a shared circuit through which the output clock signal is provided. An enable circuit is configured to cause the frequency divider to alternate between providing the common frequency clock signal as the output clock signal through the first circuit and the reduced frequency clock signal as the output clock signal through the second circuit.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Tyler J. Gomm
  • Patent number: 10833668
    Abstract: A plurality of lower voltage metal oxide semiconductor sensors are integrated and distributed in various parts of a power MOSFET to provide over temperature protection. The sensors are sensitive to temperatures of the various parts of the power MOSFET and configured to regulate the power MOSFET when a trip temperature is reached by reducing the operation of the MOSFET. A bias network is configured to set the trip temperature. In some configurations, a threshold voltage is used to monitor and control the maximum temperature.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: November 10, 2020
    Assignee: Analog Devices International Unlimited Company
    Inventors: Chiong Yew Lai, Javier A. Salcedo
  • Patent number: 10833674
    Abstract: A switch device including a switch circuit and switch controller. The switch circuit comprises first and second switches to selectively enable a path between an input terminal and an output terminal. The switch controller refers to a selection signal and a switch signal to respectively generate a first switch control signal at a first switch control signal output terminal and a second switch control signal at a second switch control signal output terminal. When the voltage level of an input signal at the input terminal is larger than a power voltage, the switch controller generates the first switch control signal and the second switch control signal capable of turning off the switch circuit. When the voltage level of the input signal is not larger than the power voltage, the switch controller generates the first switch control signal and the second switch control signal according to the switch signal.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: November 10, 2020
    Assignee: Faraday Technology Corp.
    Inventors: Feng Xu, Shu Dong Wu, Zhen Liang Zhang
  • Patent number: 10833677
    Abstract: According to the invention, only one type of enhancement MOS transistor type is used in implementing typical Boolean functions in hardware. Preferably, the MOS transistor type allows back bias control for adjusting and compensating the operation conditions. When implemented in PMOS only transistors, the pull-down functionality is performed by a single transistor with its gate and source connected to the output. This type of connection ensures that the pull-down functionality is performed by the leakage current of the pull-down transistor. The leakage currents of all the pull-up transistors need to be smaller than this pull-down current when all the pull-up paths are off. The ratio of these off-currents can be adjusted by the aspect ratios of the transistors. The logic type offers extremely low current consumption with low voltages and offers the possibility to avoid more complex shut-down circuitry often used in ultra low-power designs.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: November 10, 2020
    Inventor: Ari Paasio
  • Patent number: 10833664
    Abstract: An apparatus for delaying a signal transition is disclosed. The apparatus includes a first circuit coupled to a first power supply signal and a second, different power supply signal. The first circuit may be configured to, based on a voltage level of a logic signal, sink a current from an intermediate circuit node. A value of the current may be based upon a voltage level of the second different power supply signal. The apparatus also includes a second circuit coupled to the first power supply signal. The second circuit may be configured to generate an output signal based upon a voltage level of the intermediate circuit node. An amount of time between a transition of the logic signal and a corresponding transition of the output signal may be based on an amount of the current.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: November 10, 2020
    Assignee: Apple Inc.
    Inventors: Greg M. Hess, Hemangi U. Gajjewar, Sachmanik Cheema
  • Patent number: 10833656
    Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to determine when one or more duty cycle calibration (DCC) conditions are met. When the DCC condition(s) are met, the clock distortion calibration circuitry is configured adjust a trim value associated with at least one of first and second duty cycles of first and second voltage signals, respectively. In some embodiments, the clock distortion calibration circuitry is configured to calibrate at least one of the first and the second duty cycles of the first and the second voltage signals using the adjusted trim value to account for duty cycle distortion encountered across various voltages and/or temperatures while the electrical circuit devices and/or systems remain in a powered on state.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Qiang Tang
  • Patent number: 10832915
    Abstract: A semiconductor device, method of manufacture of a semiconductor device, and electronic system are disclosed. For example, the semiconductor device includes at least one trench disposed in a semiconductor substrate of the semiconductor device, wherein the semiconductor substrate has a first conductivity type. The semiconductor device further includes a polysilicon depleted gate shield disposed in the at least one trench, wherein the polysilicon depleted gate shield has a second conductivity type. The semiconductor device also includes a drift region disposed in the semiconductor substrate adjacent to at least one sidewall of the at least one trench, wherein the drift region has the first conductivity type, and a polysilicon gate disposed over the depleted gate shield in the at least one trench.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 10, 2020
    Assignee: Great Wall Semiconductor Corporation
    Inventor: Patrick M. Shea
  • Patent number: 10825926
    Abstract: A semiconductor device, method of manufacture of a semiconductor device, and electronic system are disclosed. For example, the semiconductor device includes at least one trench disposed in a semiconductor substrate of the semiconductor device, wherein the semiconductor substrate has a first conductivity type. The semiconductor device further includes a polysilicon depleted gate shield disposed in the at least one trench, wherein the polysilicon depleted gate shield has a second conductivity type. The semiconductor device also includes a drift region disposed in the semiconductor substrate adjacent to at least one sidewall of the at least one trench, wherein the drift region has the first conductivity type, and a polysilicon gate disposed over the depleted gate shield in the at least one trench.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 3, 2020
    Assignee: Great Wall Semiconductor Corporation
    Inventor: Patrick M. Shea
  • Patent number: 10823765
    Abstract: A low power comparator and a self-regulated device for adjusting power saving level of an electronic device are provided. The low power comparator includes an input differential pair circuit, a self-regulated device, and a tail current switch. The input differential pair circuit is configured to receive input signals to be compared. The self-regulated device is coupled to the input differential pair circuit and includes a self-regulated circuit which has a first transistor with a first threshold voltage and a second transistor with a second threshold voltage and is configured to adjust a power saving level of the low-power comparator according to the first threshold voltage and the second threshold voltage. The tail current switch is coupled to the input differential pair circuit through the self-regulated circuit to provide a constant current to the input differential pair circuit.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chow Peng, Chung-Peng Hsieh
  • Patent number: 10826403
    Abstract: A system includes an input voltage supply and a switching converter coupled to the input voltage supply. The switching converter includes a transformer having a primary coil and a secondary coil. The switching converter also includes a Y-rated capacitor with a top plate and a bottom plate, wherein the top plate is coupled to a first end of the secondary coil. The switching converter also includes a push-pull current source coupled to the bottom plate of the Y-rated capacitor. The switching converter also includes a controller coupled to the push-pull current source.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: November 3, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Yogesh Kumar Ramadass, Ashish Kumar
  • Patent number: 10826489
    Abstract: The present disclosure relates to a structure including a voltage selection circuit which includes a first device and a second device, the voltage selection circuit is configured to output a higher voltage of a first supply voltage and a second supply voltage through one of the first device and the second device, and a voltage difference between the first supply voltage and the second supply voltage is less than a threshold voltage.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: November 3, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Joseph F. Stormes, John A. Fifield, Darren L. Anand
  • Patent number: 10819333
    Abstract: A timing controller resetting circuit including: a resistor connected to an output node from which a reset signal is output and a first voltage source which supplies a first voltage; a capacitor connected to the output node and a second voltage source which supplies a second voltage that is lower than the first voltage; a reference voltage source configured to generate a reference voltage that is lower than the first voltage and higher than the second voltage; a comparator including a first input terminal which receives the first voltage, a second input terminal which receives the reference voltage, and an output terminal which outputs a comparison result signal generated by comparing the first voltage with the reference voltage; and a transistor including a first terminal which is connected to the output node, a second terminal which receives the second voltage, and a gate terminal which receives the comparison result signal.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: October 27, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ga-Na Kim, Po-Yun Park, Hong-Kyu Kim, Myeongsu Kim, Dongwon Park
  • Patent number: 10819326
    Abstract: The present invention relates to a digital clock generation apparatus. The digital clock generation apparatus is directed to providing a digital clock generation apparatus in which hardware is simple, duty cycles are easily controlled, and various duty cycles and various frequency clocks (n× clocks) are provided as compared to a 1× single-phase clock generation apparatus or a 1× multi-phase clock generation apparatus based on the conventional programmable delay element chain.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: October 27, 2020
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yil Suk Yang, Hyun Joong Lee, Chang Han Je, Jong Dae Kim
  • Patent number: 10819294
    Abstract: A circuit includes first and second gain stages and an output transistor. The second gain stage includes a transconductance amplifier and a variable impedance circuit coupled to an output of the transconductance amplifier. The variable impedance circuit is configured to implement a first impedance level at frequencies below a first frequency threshold and to implement a second impedance level at frequencies above a second frequency level. The first impedance level is larger than the second impedance level. The output transistor has a control input coupled to the variable impedance circuit. At frequencies above the second frequency threshold, the second impedance level is configured to be inversely related to current through the output transistor.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: October 27, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sovan Ghosh, Amal Kumar Kundu, Laxmi Vivek Tripurari, Anand Subramanian
  • Patent number: 10819348
    Abstract: A system of referenceless clock and data recovery and a frequency detector thereof has been provided. The output clock of the system initially works at the lowest frequency, the frequency of the output clock is monotonically increased in accordance with the control of the frequency detector, thereby gradually approximating a target value. The edge extraction circuit receives the data signal and the clock signal, identifies the transition edges of the signals and generates a data transition signal and a clock transition signal representing the transition edges of the data signal and the transition edges of the clock signal respectively. The edge detector then determines the data period of the data signal and the clock period of the clock signal. When the data period is smaller than half of the clock period, the edge detector generates a frequency-up signal and the frequency of the output clock is increased.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: October 27, 2020
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventor: Wei-Zen Chen
  • Patent number: 10819329
    Abstract: The present disclosure relates to a power supply device for a protective relay. The power supply device comprises a power circuit for supplying a power to the control circuit, wherein the power circuit includes: a semiconductor switch element having an input terminal connected to a first node for receiving a direct current, and an output terminal connected to a reference node, wherein the reference node has a voltage lower than a voltage of the first node; and a first voltage drop element disposed between the first node and a second node, wherein the second node is connected to a switching terminal of the semiconductor switch element.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: October 27, 2020
    Assignee: LSIS CO., LTD.
    Inventor: Young-Joo Lee
  • Patent number: 10812059
    Abstract: A comparator is disclosed, for comparing a first input voltage with a second input voltage and generating a corresponding output voltage. The comparator includes a follower stage coupled to a first supply rail and a second supply rail, a follower stage input terminal for the second input voltage, and a follower stage output terminal. The comparator also includes an inverter stage comprising a first inverter stage supply terminal coupled to the first supply rail, a second inverter stage supply terminal coupled to the follower stage output terminal, an inverter stage input terminal for the first input voltage, and an inverter stage output terminal for providing an inverter stage output voltage having a first range. A signal conditioning means is coupled to the inverter stage output terminal and generates a comparator output voltage at a comparator output terminal having a second range larger than the first range.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: October 20, 2020
    Assignee: Pragmatic Printing LTD
    Inventor: Joao De Oliveira
  • Patent number: 10811961
    Abstract: A charge pump includes a first power source having a voltage VREG generated from a regulated and circuit-limiter supply, a second power source having a voltage VBRG and a top-off capacitor adapted to be charged to a voltage of the high of VREG or VBRG to a limit of a voltage clamp across the top-off capacitor.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: October 20, 2020
    Assignee: Allegro MicroSystems, LLC
    Inventors: Thomas Ross, Aldo Togneri, James McIntosh, Gianluca Allegrini