Abstract: A gate driver for driving a gate of a switching element in accordance with an input signal is provided. The gate driver is configured to change a gate driving condition in accordance with a detected value of power supply voltage. Each time when the switching element is turned off, the gate driver stores a time width from a time when the input signal is switched to an off command to a time when switch-off surge occurs in the switching device. If it is determined that the gate driving condition should be changed during turn-off operation of the switching element, the gate driver switches the gate driving condition when a time corresponding to the time width stored at a previous turn-off is elapsed after a current turn-off of the switching element is started.

Abstract: An object of the present invention is to reduce the possibility of failure in the detection of metallic foreign object. A metallic foreign object detector includes a sensor part having at least one antenna coil that receives a magnetic field or current to generate a vibration signal a vibration time length measurement circuit that measures a vibration time length indicating the length of time required for the vibration of the vibration signal output from the sensor part corresponding to a predetermined wavenumber larger than 1, and a determination circuit that determines the presence/absence of a metallic foreign object approaching the antenna coil based on the vibration time length and a criterion vibration time length which is the vibration time length obtained in the absence of the approaching metallic foreign object.

Abstract: Implementation of large temperature-insensitive resistance in CMOS using short-duty-clock cycle is provided herein. Operations of a method can comprise boosting a resistance level of a switched-resistor circuit to a defined resistance level. The boosting can comprise using a short-duty-cycle clock to facilitate the boosting. Also provided is a sensor system that can comprise a short-duty-cycle clock and a switched-resistor circuit. The short-duty cycle clock boosts a resistance level of the switched-resistor circuit to a defined resistance level.

Abstract: An enhancement mode GaN FET based gate driver circuit including an active pre-driver to drive a high-slew rate, high current output stage GaN FET. Due to the active driver current from the pre-driver, the output stage pull-up FET can turn on faster as compared to a pre-driver that utilizes a passive pull-up load. The active pre-driver must provide a voltage to drive the gate of the output stage pull-up FET which is higher than the normal supply voltage to enable the maximum output level of the driver FET to approach the normal supply voltage. A feedback circuit is included in the active pre-driver to avoid the need for two supply voltages.

Abstract: A semiconductor integrated circuit includes a first signal transmission path and a second signal transmission path in parallel with each other, a first variable delay circuit provided on the first signal transmission path and configured to cause a first signal to be delayed by a first delay amount, a duty adjustment circuit provided on the first signal transmission path in series with the first variable delay circuit, and a second variable delay circuit provided on the second signal transmission path and configured to cause a second signal to be delayed by a second delay amount. The first delay amount is smaller than the second delay amount by a third delay amount corresponding to an amount of delay applied to the first signal by the duty adjustment circuit.

Abstract: An RF energy harvesting apparatus comprising an energy harvesting antenna carried on a substrate for fixing the antenna to an electrical device, wherein the antenna comprises a coil of conductive material carried on the substrate, wherein the coil provides two loops of conductive material on the substrate, the coil comprising a second loop inside a first loop; and wherein the coil comprises at least one segment arranged to reduce spatial variations in the H-field in an area circumscribed by the first loop.

Abstract: A filter includes a filter circuit, a first processing circuit, and a second processing circuit. The filter circuit receives an input signal from an input node of the filter, and converts the input signal into a voltage output. The first processing circuit provides a first control voltage to an output node of the filter according to the voltage output, wherein the first control voltage is derived from an alternating current (AC) component of the voltage output. The second processing circuit provides a second control voltage to the output node of the filter according to the voltage output, wherein the second control voltage is derived from applying DC level shift to a direct current (DC) component of the voltage output.

Abstract: A comparator circuit includes a differential input circuit, a load circuit, a first current source, a first bias voltage supplying circuit, a third connection circuit, and a fourth connection circuit. The differential input circuit includes a first transistor to which a first input signal is supplied and a second transistor to which a second input signal is supplied. The load circuit includes a third transistor connected to the first transistor through a first connection circuit and a fourth transistor connected to the second transistor through a second connection circuit, gates of the third and fourth transistors being connected to the first connection circuit through a third capacitor. The first bias voltage supplying circuit supplies a first bias voltage to the gates of the third and fourth transistors and the third capacitor.

Abstract: In one general aspect, a level-shifting circuit includes a first supply terminal configured to receive a first supply voltage, and a second supply terminal configured to receive a second supply voltage different from the first supply voltage. The level-shifting circuit includes a shifting circuit having electrical connections to an input terminal and an output terminal and configured to, in response to a first voltage at a first node, produce a second voltage at a second node. The shifting circuit is used to shift a first voltage level to a second voltage level. The level-shifting circuit includes a clamping circuit having an electrical connection to the first node where the clamping circuit is configured to limit current at the first node from flowing to a ground.

Abstract: Apparatus for use in a microgrid, which comprises a DC bus with at least one DC power source connected thereto, an AC bus connected to a mains power grid that supplies the microgrid, and a DC/AC converter coupling the DC bus and the AC bus, wherein the DC/AC converter may be a one-way DC/AC inverter or a bidirectional DC/AC converter, the apparatus comprising a control system, which is configured to control number (at least one) DC power converters, each of which is configured to couple a respective controllable DC load to the DC bus, and to control the power flowing from the DC bus to each of the number controllable DC loads, so as to control each of the number controllable DC loads to fulfil its function and the voltage on the DC bus.

Abstract: The present description relates to a wireless power transmission/reception device. The present description provides a magnetic field controlling member for focusing a magnetic field between a primary coil, which is connected to a power source of a wireless power transmission system and forms a magnetic field, and a secondary coil which is for receiving power by means of the magnetic field. The magnetic field controlling member includes: a substrate, between the primary coil and secondary coil, of which one side faces the primary coil or secondary coil; a pattern unit which is placed on the substrate and has a plurality of thin films that are positioned at a predetermined distance away from each other; and a connecting unit which electrically connects the plurality of thin films.

Abstract: Circuits and methods for delay mismatch compensation are described. A circuit may comprise multiple data paths between a signal source, such as a driver, and a load. The paths may have different lengths, thus causing delay mismatches. An exemplary circuit of the type described herein may comprise delay elements and at least one feedback circuit designed to compensate for such delay mismatches. The circuit may operate in different phases, such as a compensation phase and a driving phase. In the compensation phase, rings oscillators including delay elements and the at least one feedback circuit may be formed. In this phase the delay may be adjusted to compensate for mismatches. In the driving phase, the signal source may be connected to the load.

Abstract: A foreign object detection device for a wireless power transfer system includes a storage unit that stores first coil device information including a shape and a size of a first coil facing surface, a height position from the reference surface, and a height position of a first device facing surface; an information acquiring unit that acquires second coil device information including a shape, a size, and a height position of a second coil facing surface, and a height position of a second device facing surface; a region identifying unit that identifies a magnetic field generation region generated between the first device facing surface and the second device facing surface during power feeding, based on the first coil device information and the second coil device information; and a foreign object detection unit that detects the presence or absence of a foreign object within the identified magnetic field generation region.

Abstract: A compensation device for compensating PVT variations of an analog and/or digital circuit. The compensation device includes a transistor having a first terminal, a second terminal, a third terminal, and a fourth terminal allowing to modify a threshold voltage of the transistor. The transistor is configured to be in saturation region. The voltage at the third terminal has a predetermined value and the difference between the voltage at the second terminal and the voltage at the third terminal has a predetermined value. A current generation module is configured to generate a current of a predetermined value. A compensation module is configured to force this current to flow between the first terminal and the third terminal by adjusting the voltage of the fourth terminal.

Abstract: An apparatus includes a power converter and a controller. The power converter converts a received input voltage into an output voltage that powers a dynamic load. The controller controls a setting of a switching frequency applied to the power converter. During one operational mode, the controller transitions a setting of the switching frequency of the power converter from a first clock frequency signal to a second clock frequency signal depending on occurrence of phase alignment of the second clock frequency signal and the first clock frequency signal, which may eventually occur over multiple switching control cycles. Transition of the switching frequency from the first clock frequency signal to the second clock frequency signal at or around a time of the phase alignment reduces possible perturbations in the output voltage as a result of the clock frequency switchover.

Abstract: Methods and apparatuses are provided for aligning read data in a stacked semiconductor device. An example apparatus includes a stacked semiconductor device comprising stacked first and second die. The stacked semiconductor device includes a first path having a first align (first die) and second align (second die) circuits for providing read data from the second die and a second path having a first replica align (first die) and second replica align (second die) circuits. During a timing align operation, a first control circuit sets the first align and replica align circuits to a first delay value based on a propagation delay of a clock signal through the second replica align circuit. After setting of the first delay value, a second control circuit sets the second align and replica align circuits to a second delay value based on a difference in propagation delays through the first and second replica align circuits.

Abstract: A phase locked loop circuit includes a voltage controlled oscillator configured to output a clock signal having a predetermined frequency based in a control voltage, a phase frequency detector configured to compare the clock signal with a reference signal to output a first control signal and a second control signal, a charge pump configured to output the control voltage based on the first control signal and the second control signal, a voltage supply including an output terminal connected to an output terminal of the charge pump by a transmission switch, and a leakage remover circuit connected to the transmission switch and configured to remove a leakage current flowing through the transmission switch while the transmission switch is turned-off.

Abstract: The disclosure provides a delay line circuit including an output stage. The output stage includes a first inverter cell, a second inverter cell, a correction circuit, and a first switch capacitor array. The input terminal of the first inverter cell receives a reference clock signal. The input terminal of the second inverter cell is coupled with the output terminal of the first inverter cell. The first terminal of the correction circuit is coupled with the output terminal of the first inverter cell, and the second terminal of the correction circuit is coupled with a ground, wherein the correction circuit corrects a duty cycle of the delay line circuit. The first terminal of the first switch capacitor array is coupled with the output terminal of the second inverter cell, and the second terminal of the first switch capacitor array is coupled with the ground.

Abstract: A system and method for efficiently retaining data in sequential elements during power down modes. In various embodiments, a master latch of a flip-flop circuit receives an always-on first power supply voltage, whereas, a slave latch and other surrounding circuitry receives a second power supply voltage capable of being powered down. During a power down mode, circuitry consumes less power while the master latch retains stored data. In some designs, the flip-flop circuit is a level shifting circuit, and the always-on first power supply voltage is less than the second power supply voltage. The master latch uses complex gates with a p-type transistor at the top of a stack of p-type transistors receiving the always-on power supply voltage level on its source terminal and the retained data value on its gate terminal. This top p-type transistor is capable of remaining disabled even when used in a level shifting manner.

Abstract: A power conversion device, that includes a drive circuit 11a that drives a switching element 4 included in an upper-arm for one of three phases, a drive circuit 11b that drives a switching element 5 included in a lower-arm for the one phase, and a control circuit 9 that transmits a control signal to the drive circuits 11a, 11b, is provided. The power conversion device includes power supply circuits 12a, 12b that provide power to the drive circuits 11a, 11b, respectively, a low-voltage power supply 6 that supplies power to one of the power supply circuits, 12a, and a high-voltage power supply 1 that supplies power to the other of the power supply circuits, 12b. Accordingly, it is possible to reliably protect a system: by realizing minimal redundancy of the power supply, the power supply generation circuit, etc.; and by realizing the short-circuit mode at the time of error occurrence.