Abstract: One or more resistors or resistances are integrated in a 7-bit DVR or PVCOM integrated circuit. A 7-bit DVR or PVCOM integrated circuit includes a 7-bit DAC. The integrated resistors or resistances (R1, R2, or RSET, or any combination) reduces the number of external components, reduces the number of pins, and increases the accuracy of the DVR or PVCOM circuit. The least significant bit (LSB) of the DAC depends only on ratios of internal resistors, which can be made very accurate and independent of temperature.

Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.

Abstract: A method of quantum processing using a quantum processor comprising a plurality of Kerr non-linear oscillators (KNOs), each operably drivable by both i) a controllable single-boson drive and ii) a controllable two-boson drive, the method comprising simultaneously controlling a drive frequency and a drive amplitude of the controllable single-boson drives to define a problem and controlling a drive frequency and a drive amplitude of the two-photon drives to define the Hilbert space, including increasing the amplitude of the two-boson drive and reaching both amplitude conditions a) 4 times the amplitude of the two-boson drives being greater than the loss rate, and b) the amplitude of the two-boson drives being greater than the amplitude of the single-boson drive, and maintaining both amplitude conditions a) and b) until a solution to the problem is reached; and reading the solution.

Abstract: A voltage regulator includes first and second bias circuits, a transistor, and a load prediction circuit. The transistor has a first current electrode coupled to a first power supply voltage terminal, a second current electrode for providing a regulated output voltage, and a control electrode. The first biasing circuit is for providing a first bias voltage to the control electrode of the transistor in response to a feedback signal generated from the regulated output voltage. The second biasing circuit is for providing a second bias voltage to the control electrode of the transistor in response to a control signal. The load current prediction circuit is coupled to the second biasing circuit. The load prediction circuit is for providing the control signal to the second biasing circuit in response to determining that a load current at the second current electrode is expected to increase.

Abstract: A controller is configured to select a rate of change direction of an output voltage of a variable voltage converter (VVC) based on a direction of current flow associated with a capacitor of the VVC, and to adjust a magnitude of the rate of change direction based on directions of current flow associated with the capacitor and an electric machine coupled to the VVC.

Abstract: A current sense circuit for a pass transistor is described. The circuit comprises a sense transistor having input and control ports that are coupled to input and control ports respectively of the pass transistor. The circuit comprises a differential amplifier comprising a differential input and output. An output port of the pass transistor is coupled to a first port of the differential input and an output port of the sense transistor is coupled to a second port of the differential input. The differential amplifier comprises a first sub-amplifier and a second sub-amplifier that are arranged in parallel and which are operated in an auto-zero phase and in an amplification phase in an alternating manner, and which are operated in the auto-zero phase in a mutually exclusive manner. The output of the differential amplifier is used to control voltage drops across the sense transistor and the pass transistor.

Abstract: According to one embodiment, a gate control circuit includes a controller, a delay circuit, a power circuit, a boosting circuit, a first transistor, and a control circuit. The controller outputs first and second control signals based on a control signal from outside. The delay circuit delays the first control signal. The power circuit is capable of controlling a power supply voltage to be output based on the delayed first control signal. The boosting circuit is capable of boosting and outputting an input voltage. The first transistor has one end connected to an output node of the boosting circuit, and the other end grounded. The control circuit is capable of controlling a gate voltage of the first transistor based on the second control signal.

Abstract: A frequency converter comprising a frequency transposition block for samples (11Q_1, 11Q_2), a filtering block (12Q_1, 12Q_2), the filtered samples y(n) verifying y(n)=c(0)·x(n)+c(1)·x(n?1)+c(2)·x(n?2)+ . . . +c(p?1)·x(n?p+1)+c(p)·x(n?p)+c(p?1)·x(n?p?1)+ . . . + . . . +c(1)·x(n?2·p+1)+c(0)·x(n?2·p), wherein x( ) are the transposed samples and c(0), . . . c(p) are the real coefficients of the filter; and being adapted for, during a cycle for determining the value of the filtered sample y(n): calculating the first terms c(0)·x(n), c(1)·x(n?1), c(2)·x(n?2), . . . , c(p)·x(n?p) by multiplying the respective coefficients and transposed samples, and storing in memory said first calculated terms; reading the second terms c(p?1)·x(n?p?1), . . . , c(1)·x(n?2·p+1), c(0)·x(n?2·p), calculated and stored in memory during previous cycles for determining the value of filtered samples y(n?m); and determining y(n) by summation of the first and second terms.

Abstract: According to a first aspect of the present inventive concept there is provided an equalizer system comprising a decision feedback equalizer (DFE), the DFE comprising: a static comparator configured as a decision device of the DFE; and a feedback path comprising a set of filter taps including at least a first filter tap; wherein the static comparator presents hysteresis and wherein a tap coefficient of the first filter tap is set such that an input signal level of the static comparator is shifted to compensate for the hysteresis.

Abstract: A control portion and semiconductor switches included in a power supply system function as a current control device. The source of the semiconductor switch is connected to the source of the semiconductor switch. The two semiconductor switches connect the respective positive electrodes of a first power storage element and a second power storage element to each other. The control portion controls a current flowing between the drains of the two semiconductor switches by substantially simultaneously turning on or off the two semiconductor switches. The respective breakdown voltages between the drain and the source of the two semiconductor switches are different from each other.

Abstract: Techniques for providing an enhanced resonant circuit amplifier are described herein. Using a capacitor to couple the drive to the resonant circuit can be problematic because the current flows the same direction with every energy burst, which causes the coupling capacitor to charge up and stop injecting energy into the resonant circuit. To solve this issue, embodiments disclosed herein add a burst of energy once every half cycle. This reduces distortion in the resonant energy. A second benefit is the ability to “push in” and “pull out” energy from the resonant circuit, which can prevent the capacitor from charging up and allow a resonant circuit amplifier to continually produce a symmetric, stable output. In addition, a controller can dynamically modify a number of aspects of an output, e.g., an amplitude and/or a DC bias, by modifying the duty cycle of an input signal.

Abstract: A method is used to control an electronic device that includes a switching unit having a main MOS transistor having a substrate, a first conducting electrode and a second conducting electrode coupled to an output terminal. The method includes controlling the main transistor in such a way as to put it into an on state or an off state such that, when the main transistor is in the on state, the substrate and the first conducting electrode of the main transistor are connected to an input terminal and, when the main transistor is in the off state, the first conducting electrode of the main transistor is isolated from the input terminal and a first bias voltage is applied to the first conducting electrode and a second bias voltage is applied to the substrate of the main transistor.

Abstract: A circuit has first and second semiconductor switches, each of which has a load path and control terminal connected in series. Each switch includes a first semiconductor device having a load path and a control terminal coupled to the control terminal of its switch, and a second semiconductor device having a load path between first and second load terminals, and a control terminal. Each second semiconductor device has its load path connected in series to the load path of the corresponding first semiconductor device. The semiconductor devices are coupled such that the second semiconductor devices are controlled by a load path voltage of the first semiconductor devices. The switches are integrated in a common semiconductor body. The first switch is implemented in a first area of the semiconductor body, and the second switch is implemented in a second area. In a horizontal plane, the first area surrounds the second area.

Abstract: A semiconductor integrated circuit includes an output circuit driven by a power voltage across a first and a second node. A control circuit is driven by the power voltage to control output a digital signal at a pad terminal, a logic value of the signal being set by a core circuit connected to the output circuit. The digital signal causes a voltage at the first node to be high and a voltage at the second node to low when a predetermined power voltage higher than a withstanding voltage of the output circuit is applied across the first and second nodes. The control circuit controls voltages across terminals of switching elements in the output circuit to be less than their withstanding voltages and to prevent current flowing from the pad terminal to the output circuit when the first power node is in a high impedance state.

Abstract: A driving device includes: a driving circuit operating with a single power supply in accordance with a driving signal; a first parallel circuit formed of a first capacitor and a first zener diode connected together in parallel, and having a first end connected to an output terminal of the driving circuit; a series circuit connected between a second end of the first parallel circuit and a ground of the driving circuit, and formed of a diode and a second parallel circuit (of a second capacitor and a second zener diode) connected to each other in series; and a resistor is connected between the second end of the first parallel circuit and the ground of the driving circuit. A voltage across the resistor is used as an output voltage for driving the insulated gate semiconductor element. A voltage across the first capacitor is superimposed negative-wise on the output voltage.

Abstract: An energy harvesting interface receives an electrical signal from an inductive transducer and outputs a supply signal. An input branch includes a first switch and a second switch connected in series between a first input terminal and an output terminal, and further a third switch and a fourth switch connected in series between a second input terminal and the output terminal. A first electrical-signal-detecting device coupled across the second switch detects a first threshold value of an electric storage current in the inductor of the transducer. A second electrical-signal-detecting device coupled across the fourth switch detects whether the electric supply current that flows through the fourth switch reaches a second threshold value lower than the first threshold value.

Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.

Abstract: A transformer based digital isolator is provided that has improved immunity to common mode interference. The improved immunity is provided by placing the transformer in association with an H-bridge drive circuit, and taking additional effort to tailor the on state resistance of the transistors to control a common mode voltage at the transformer.

Abstract: According to one embodiment, a compact low-power receiver comprises first and second analog circuits connected by a digitally controlled interface circuit. The first analog circuit has a first direct-current (DC) offset and a first common mode voltage at an output, and the second analog circuit has a second DC offset and a second common mode voltage at an input. The digitally controlled interface circuit connects the output to the input, and is configured to match the first and second DC offsets and to match the first and second common mode voltages. In one embodiment, the first analog circuit is a variable gain control transimpedance amplifier (TIA) implemented using a current mode buffer, the second analog circuit is a second-order adjustable low-pass filter, whereby a three-pole adjustable low-pass filter in the compact low-power receiver is effectively produced.

Abstract: A semiconductor device includes a gate terminal, a ground terminal, a power-supply terminal, and a source terminal. The semiconductor device includes a first switch element having a gate and a source, the first switch element connected between the gate terminal and the source terminal, a second switch element connected between one of the gate of the first switch element and the source terminal or between the gate of the first switch element and the ground terminal and configured to switch the first switch element between turned-on and turned-off states, and a capacitor having one terminal thereof connected to the power-supply terminal and the ground terminal and another terminal thereof connected to the gate of the first switch element. Based on the potential state of the ground terminal and the state of the second switch element, the capacitor boosts the voltage of the gate of the first switch element.