Abstract: An integrated circuit includes a differential signal driver that receives a first signal from a first input terminal, receives a second signal, which is a differential signal of the first signal, from a second input terminal, outputs a first output signal corresponding to the first signal to a first output terminal, and outputs a second output signal corresponding to the second signal to a second output terminal.

Abstract: Certain aspects of the present disclosure generally relate to generating a large electrical resistance. One example circuit generally includes a first transistor having a gate, a source connected with a first node of the circuit, and a drain connected with a second node of the circuit. The circuit may also include a voltage-limiting device connected between the gate and the source of the first transistor, wherein the device, if forward biased, is configured to limit a gate-to-source voltage of the first transistor such that the first transistor operates in a sub-threshold region. The circuit may further include a second transistor configured to bias the voltage-limiting device with a current, wherein a drain of the second transistor is connected with the gate of the first transistor, a gate of the second transistor is connected with the first node, and a source of the second transistor is connected with an electric potential.

Abstract: An apparatus for coupling to capacitors to form a charge pump includes first and second sets of switch elements, and a controller. Switches in the first set couple terminals of capacitors to permit charge transfer between them. Switches in the second set couple terminals of at least some of the capacitors to either a high-voltage or a low-voltage terminal. The controller causes the switches to cycle through a sequence of states, each defining a corresponding configuration of the switch elements. At least three of the states define different configurations permitting charge transfer either between a first capacitor and a second capacitor, or between a first capacitor and one of the terminals. The configured cycle of states causes voltage conversion between the two terminals.

Abstract: A determination circuit of one embodiment includes first and second inverter circuits, a first transistor which turns on when receiving an asserted first signal, and a first capacity component including a first end which receives an inversion signal of the first signal. The second inverter circuit includes an input coupled to an output of the first inverter circuit, and includes an output coupled to an input of the first inverter circuit. The first node is coupled to a first potential node, the first transistor is coupled between the second node and a second potential node having a lower potential than a potential of the first potential node, and a second end of the first capacity component is coupled to the second node.

Abstract: The present application discloses a converter system, a driving circuit and a driving method for a semiconductor switch. The driving circuit includes a driving unit, a sampling unit and a selection unit. A plurality of turn-off driving units with different turn-off parameters is provided in the driving unit, and a turn-off driving unit having a turn-off parameter adaptive to the working state of the semiconductor switch is selected according to the working state of the semiconductor switch so as to turn off the semiconductor switch.

Abstract: A synchronous clock edge alignment system and method increases detection coverage of transition delay faults that occur in logic circuits that have data released by a clock at an input of logic circuits internal to an integrated circuit and/or released at the output of the logic circuits when testing an integrated circuit. To increase detection coverage of inter-clock transition delay faults, in at least one embodiment, the synchronous clock edge alignment system and method align same transition type edges of internal data releasing clock signals, and at least two of the clock signals have different frequencies. By aligning the edges of the clock signals, transition delay faults that might otherwise not have occurred can be detected by, for example, a conventional circuit testing apparatus. Thus, aligning the edges of the clock signals increases detection of inter-clock transition delay faults.

Abstract: In a step-up circuit, which is an electronic control device, changes in current caused by a current rise when stepping up is started and a current drop when stepping up is stopped generate magnetic induction noise due to fluctuations in the electromagnetic induction voltage in signal lines around the step-up circuit. The present invention is a step-up circuit for stepping up by current control, wherein the step-up circuit is provided with a plurality of target current values for retaining a step-up current so that the current is raised in a stepwise manner when stepping up is started and dropped in a stepwise manner when stepping up is stopped. The present invention reduces electromagnetic induction noise generated by the changes in current when stepping up is started and when stepping up is stopped.

Abstract: An integrated circuit controls one or more external back-to-back (anti-series) transistor switches with three pins per switch. Two pins couple the switch terminals of the external switch to terminals of an internal anti-series switch. An intermediate source node of the internal switch provides a reference voltage that is representative of the external switch's intermediate source node. A predriver of the integrated circuit drives a gate signal relative to the reference voltage, enabling fast, non-dissipative switching of the external switch. A disclosed method includes coupling switch terminal signals from an external anti-series switch to terminals of an internal anti-series switch; and driving a gate signal to the external anti-series switch relative to a reference voltage of an intermediate node of the internal anti-series switch.

Abstract: A power switch circuit includes a first transistor, a second transistor and a current source. A first source/drain terminal and a gate terminal of the first transistor receive a first supply voltage and a second supply voltage, respectively. A second source/drain terminal and a body terminal of the first transistor are connected with a node z. An output signal is outputted from the node z. A first source/drain terminal and a gate terminal of the second transistor receive the second supply voltage and the first supply voltage, respectively. A second source/drain terminal and a body terminal of the second transistor are connected with the node z. The current source is connected between a bias voltage and the node z. The first supply voltage, the second supply voltage or the bias voltage is selected as the output signal.

Abstract: According to various embodiments, there is provided a method for generating a reference clock signal, the method including discharging a capacitive element to a discharged state, when a reset signal has a predetermined reset state; charging the capacitive element from the discharged state to a first voltage, when a charge signal has a predetermined charge state; comparing the first voltage to a zero voltage, when a compare signal has a predetermined compare state; generating a second voltage based on the comparing of the first voltage to the zero voltage; generating a clock signal based on the second voltage, using an oscillator; and generating each of the reset signal, the charge signal and the compare signal, based on the clock signal.

Abstract: A primary circuit outputs, in response to an input signal, a first signal with a first reference potential. A level shift main circuit converts the reference potential of the first signal received from the primary circuit to a second reference potential to output a second signal with the second reference potential. A secondary circuit generates an output signal with the second reference potential using the second signal. At least one rectifying element circuit is provided between the primary circuit and the secondary circuit. At least one of the primary circuit and the secondary circuit includes at least one detection circuit detecting a change in a current flowing through the rectifying element circuit to determine whether a potential corresponding to the second reference potential is lower than or equal to a potential corresponding to the first reference potential.

Abstract: The current-to-voltage converter includes an input for the current to be converted, an output for the converted voltage, a current-to-voltage conversion resistor arranged between the output and a reference potential, a processing circuit including a transistor, the input being connected to the output via the transistor, a twin circuit including components identical to and disposed in a similar way to those of the processing circuit, a voltage follower connected at the input to the processing circuit and at the output to the twin circuit, and means for reinjecting the current at the output of the follower into the processing circuit.

Abstract: An apparatus of performing a clock skew adjustment between at least first and second clock signals includes first and second skew sensors and a skew controller. The first skew sensor receives a third clock signal obtained by delaying the first clock signal by a first delay and a fourth clock signal obtained by delaying the second clock signal by a second delay, and generates first information based on the third and fourth clock signals. The second skew sensor receives a fifth clock signal obtained by delaying the first clock signal by a third delay and a sixth clock signal obtained by delaying the second clock signal by a fourth delay, and generates second information based on the fifth and sixth clock signals. Each of the first and second information varies depending on the clock skew. The skew controller performs the clock skew adjustment based on the first and second information.

Abstract: An embodiment circuit includes a first voltage-controlled delay line (VCDL), a second VCDL, and a first flip-flop. The first VCDL includes a first input terminal configured to receive a first input voltage, and a second input terminal configured to receive a clock signal. The second VCDL includes a first input terminal configured to receive a second input voltage, and a second input terminal configured to receive the clock signal. The first flip-flop includes a reset pin coupled to an output terminal of the first VCDL, and a clock pin coupled to an output terminal of the second VCDL.

Abstract: A semiconductor device for driving a semiconductor switch, including a first transistor configured to extract gate charges of the semiconductor switch with a first extraction force, a comparator configured to compare gate voltage of the semiconductor switch with a threshold voltage to thereby output a first decision signal, an AND circuit configured to perform an AND operation on a gate voltage of the first transistor and the first decision signal to thereby output a second decision signal, a delay circuit configured to delay the second decision signal by a predetermined time and to output the delayed signal as a second control signal, and a second transistor configured to be turned-on, in response to the second control signal, the predetermined time after the first transistor is turned-on, to thereby extract the gate charges of the semiconductor switch with a second extraction force larger than the first extraction force.

Abstract: A sensorless measurement device for filter capacitor current by using a state observer is provided. The sensorless measurement device comprises a chip, wherein the chip comprises the state observer. The state observer is configured to retrieve a filter-capacitor-voltage actual value and a direct current link (dc-link) voltage of a present sampling time. According to the filter-capacitor-voltage actual value and the dc-link voltage, the state observer is configured to output a filter-capacitor-voltage state variable value, a filter-capacitor-current state variable value, and a disturbance-voltage state variable value of a next sampling time. The filter-capacitor-current state variable value is an average current value without ripples.

Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

Abstract: A constant impedance switch dynamically manages switch impedance to eliminate or substantially reduce impedance glitches during switching events by stepping variable impedances through sequences of impedance values. As a result, VSWR may be reduced to or near 1:1, allowing programming and circuitry to be simplified. Switch impedance may be maintained for single and multi-throw switches having variable impedances of any order. Each variable impedance may comprise one or more configurable cells, subcells and elements controlled by thermometer, binary, hybrid or other coding technique.

Abstract: Current-mode signaling for a one-to-many clock signal distribution providing significantly less dynamic power use and improved noise immunity compared to traditional VM signaling schemes.

Abstract: A switch drive and control arrangement may comprise a first transformer configured to receive a control signal, a second transformer configured to receive a clock signal, and a demodulator configured to receive the control signal and the clock signal from a switch controller, via the first transformer and the second transformer. The demodulator may be configured to output a demodulated signal in response to the control signal and the clock signal. A signal fault detector may be provided to determine a fault in at least one of the control signal and the clock signal. A switch may be turned off in response to a fault being detected in at least one of the control signal or the clock signal.