Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) comprises a comparator for generating a comparison value according to an analog signal; a SAR, coupled to the comparator, comprises N memory units, each memory unit storing a control value and the N control values being related to the comparison value, N being an integer greater than two; and a thermometer-coded DAC, which generates the analog signal and is coupled to the comparator and the SAR. The thermometer-coded DAC comprises N capacitors. The N capacitors are respectively coupled to the N memory units. The N terminal voltages of the N capacitors are respectively controlled by the N control values.

Abstract: A charge-redistribution successive approximation ADC includes: a comparator, generating a comparison result; a register, storing a digital output code, determining a bit value of the digital output code according to the comparison value; a control unit, generating a control signal according to the digital output code; a plurality of first capacitors, each including a first end and a second end, the first end coupled to a first input end of the comparator; at least one second capacitor, including a third end and a fourth end, the third end coupled to the first input end of the comparator. Before the voltages of the second end of each first capacitor and the fourth end of the second capacitor are switched, the second end is coupled to a first voltage and the fourth end is coupled to a second voltage different from the first voltage.

Abstract: An analog to digital converter (ADC) system includes two signal paths in parallel with each other, where the signal paths include separate ADC circuits to separately operate on a same input signal and output separate digital signals. A difference signal is calculated as a difference of the digital signals output from the two signal paths to determine an error present in one or both of the signal paths. The error may be modulated in one or both of the signal paths and demodulated from the difference signal according to a same digital modulation pattern to compute an error compensation signal to compensate for at least one of the modulated error and a secondary error resulting from the modulation of the error.

Abstract: Disclosed are methods and systems for significantly compressing sparse multidimensional ordered series data comprised of indexed data sets, wherein each data set comprises an index, a first variable and a second variable. The methods and systems are particularly suited for compression of data recorded in double precision floating point format.

Abstract: A source driver including: a current source that provides an approximately constant current; a channel coupled to a source electrode and including a digital to analog converters (DAC), the DAC including: a voltage source that applies an output voltage to the source electrode based on the approximately constant current provided by the current source; and a control unit having circuitry that: inputs a digital value; and terminates, based on the digital value, charging of the voltage source by the approximately constant current; and a calibration unit having circuitry that: generates a comparison between a test voltage applied by the voltage source with a target voltage; and modifies the approximately constant current based on the comparison.

Abstract: Systems and methods for providing search results based on time obtain an item are discussed. In an example, a method can include receiving a search query, generating search results, calculating a time to obtain for each listing in the search results, and arranging the search results for display. The search query can include a current location of a mobile device. The search results can include a plurality of listings, with each listing including a location. The locations representing either a physical location proximate the current location or a delivery time to the current location. The search results can be arranged for display in various manners according to the calculated time to obtain for each result.

Abstract: A semiconductor device is provided that includes a first chip that generates a single signal by connecting a first signal line and a second signal line, to which differential signals are respectively provided, and outputs the single signal to a third signal line. The first chip is driven by a first power supply voltage. The semiconductor device also includes a second chip comprising an analog-to-digital converter (ADC) that receives the single signal through the third signal line, compares the single signal with a reference voltage, and outputs a digital signal based on the comparison. The semiconductor device also includes a controller that monitors the digital signal and adjusts the reference voltage to be approximately equivalent to the first power supply voltage.

Abstract: A mobile communication device and a radiated power adjusting method thereof are provided. The mobile communication device includes an antenna, a signal measurement module, a proximity sensing module and a controlling module. The antenna receives a radio-frequency signal, and the signal measurement module is coupled to the antenna and measures a signal parameter of the radio-frequency signal. The proximity sensing module is switched between an activation mode and an original detection mode according to existence of an object, wherein a sensing conductor is configured adjacent to an adjusted antenna. The controlling module is coupled to the signal measurement module and the proximity sensing module, and the controlling module adjusts the radiated power of the adjusted antenna. When the signal parameter decreases more than a threshold value and the proximity sensing module is in the activation mode, the controlling module reduces the radiated power of the adjusted antenna.

Abstract: A configuration circuit for obtaining a digital code includes a controller circuit that generates a plurality of multibit control words. A digitally controlled current source circuit receives a multibit control word generated by the controller circuit. The digitally controlled current source circuit generates an output current that corresponds to the multibit control word in accordance with a predetermined output curve. A test voltage node receives the output current, and a test voltage develops in response to the output current. A reference voltage node develops a reference voltage, the level of which is independent of the multibit control word. A voltage comparison circuit (i) receives the test voltage and the reference voltage, (ii) compares the two voltages to produce a comparison result and (iii) sends the comparison result to the controller circuit. The digital code is obtained by the configuration circuit using the comparison result and the multibit control word.

Abstract: A semiconductor device according to the present invention has a capacitance DAC (Digital-to-Analog Converter) circuit and a comparator. The capacitance DAC circuit includes: first capacitors to which input signals are given and each of which has a capacitance value corresponding to a weight of a bit to be converted; and second capacitors to which common voltages are given and whose sum of capacitance values is equivalent to that of the first capacitors. Further, the second capacitors include: a redundant bit capacitor having a capacitance value corresponding to a weight of a redundant bit; and adjustment capacitors each having a capacitance value obtained by subtracting the capacitance value of the redundant bit capacitor from the sum of the capacitance values of the second capacitors.

Abstract: The present disclosure pertains to systems and methods for monitoring a plurality of analog-to-digital converters. In one embodiment, a plurality of input channels may each be in communication with a different phase of a three-phase electric power delivery system. The input channels may be configured to receive analog signals from the different phases. A composite signal subsystem may be configured to generate a composite signal based on the plurality of input channels. An analog-to-digital converter subsystem may be configured to produce a digitized representation of each of the plurality of input channels and a digitized representation of the composite signal. An analog-to-digital converter monitor subsystem may identify an error in the analog-to-digital conversion based on the digitized representation of the composite signal and the digitized representations of the plurality of input channels.

Abstract: Provided, among other things, is an apparatus for digitally processing a discrete-time signal that includes: an input line for accepting an input signal, processing branches coupled to the input line, and an adder coupled to outputs of the processing branches. First and second lowpass filters, each having a frequency response with a magnitude that varies approximately with frequency according to a product of raised functions, are included within baseband processors in such processing branches.

Abstract: A compact, low profile dipole antenna assembly includes first and second linear radiating elements that form the positive and negative sides of the dipole antenna, and a balun that extends in parallel with the second radiating element, i.e., the negative side of the dipole antenna. The second radiating element is connected to ground at one end and is an open circuit at an opposite end. A main feed line, which is part of the balun, also connects to a common ground with the second radiating element. The balun and the connection to ground act as an impedance transformer, and the second radiating element acts as the negative side of the dipole antenna as well as a ground plane for the balun. The balun and the second radiating element share a volume with the second radiating element electrically shielding the balun, and the main feed probe connecting to ground within the shared volume.

Abstract: An encoder that supports multiple code rates and code lengths is disclosed. A shift register utilized by the encoder may be scaled in size based on a selected code rate or code length. The shift register shifts a bit series for the matrix without requiring fixed feedback points within the register. The sizes of the matrix and bit series are based on the selected code rate or code length, and the encoder loads the bit series into a first portion of the shift register, and a division of the bit series into a second portion of the shift register located adjacent to the first portion. The encoder periodically repopulates the shift register from memory to simulate circular shifting of the bit series without feedback points. Accordingly, complexity of the encoder is reduced.

Abstract: Embodiments herein are directed to efficient crash recovery of persistent metadata managed by a volume layer of a storage input/output (I/O) stack executing on one or more nodes of a cluster. Volume metadata managed by the volume layer is organized as a multi-level dense tree, wherein each level of the dense tree includes volume metadata entries for storing the volume metadata. When a level of the dense tree is full, the volume metadata entries of the level are merged with the next lower level of the dense tree. During a merge operation, two sets of generation IDs may be used in accordance with a double buffer arrangement: a first generation ID for the append buffer that is full (i.e., a merge staging buffer) and a second, incremented generation ID for the append buffer that accepts new volume metadata entries. Upon completion of the merge operation, the lower level (e.g., level 1) to which the merge is directed is assigned the generation ID of the merge staging buffer.

Abstract: Computer-based systems, methods, and articles of manufacture are disclosed. In a social network embodiment, information regarding a first user is obtained and formed into a first dataset. Conceptual spaces are selected for the first user, and the first user's location is determined in the spaces. Distances between the first user and other users and their datasets are computed in the selected conceptual spaces. Actions are taken based on the distances, such as including or excluding the other users from a friends list of the first user.

Abstract: The invention provides a system for conversion between analog domain and digital domain with mismatch error shaping, including a DAC, a first injection circuit coupled to the DAC, and a second injection circuit coupled to the DAC. The DAC generates a first analog value in response to a first digital value, and generates a second analog value in response to a second digital value. The first injection circuit enables an analog injection value to be injected to the second analog value when the DAC generates the second analog value, wherein the analog injection value is converted from a digital injection value formed by a subset of bits of the first digital value. The second injection circuit injects the digital injection value to the second digital value, or combines the digital injection value and a related value obtained according to the second analog value.

Abstract: Embodiment of the disclosure may includes systems, methods, and devices for providing multidimensional search results on a plurality of search planes. Such systems, methods, and devices may: (i) receive one or more search terms from one or more user interfaces of the system; (ii) perform a search of one or more informational repositories to obtain a list of search results wherein the informational repositories may include the Internet and one or more databases; (iii) process the list of search results to classify each search result in one of a plurality of categories; (iv) cause a presentation of the search results in a plurality of search planes on the display of the system such that each search plane corresponds to one of the plurality of categories. In addition, the software applications may include a sorting software application that groups the list of search results into one of a plurality of categories.

Abstract: A first portion of a programmable switched capacitor block includes a first plurality of switched capacitors and a second portion of the programmable switched capacitor block includes a second plurality of switched capacitors. A first switch associated with the first plurality of switched capacitors as well as a second switch associated with the second plurality of switched capacitors may be configured based on a type of analog function that is to be provided. The configuring of the first analog and the second analog block may include the configuring of the first switch associated with the first plurality of switched capacitors when the analog function operates on a first single ended signal and the configuring of both the first and second switches when the analog function operates on a differential signal.

Abstract: To analyze data fields in an unstructured data set or a data set where the structure is unknown, masks can be constructed and used to determine locations of the individual fields within each data set entry. The locations can be indicated as offsets within a data set entry. An offset indicates where a data field begins. A set of masks can be constructed for at least some of the entries in a data set (e.g., a file). The masks can include a mask for padding (e.g., spaces, tabs, zeroes, etc.), and each expected type of data (e.g., alphabetic character, numeric character, and symbol). Each type of mask can be aggregated across data set entries and then analyzed to identify individual field locations. With the information about field locations, the data set can be analyzed.