Abstract: A fast latched comparator may include an amplifier portion and a latch portion. A switch activated by a reset pulse may short together outputs of the latched comparator.

Abstract: Methods and systems for clock gating are described herein. In certain aspects, a method for clock gating includes receiving an input signal of a flip-flop and an output signal of the flip-flop, and passing a clock signal to an input of a gate in the flip-flop if the input signal and the output signal have different logic values or both the input signal and the output signal have a logic value of zero. The method also includes gating the clock signal if both the input signal and the output signal have a logic value of one.

Abstract: An electronic apparatus includes a first switch unit being connected between an electrical load and a battery, a second switch unit being connected between the electrical load and the battery, and being connected in parallel with the first switch unit, a first control unit that controls the first switch unit so as to control supplying power from an external apparatus to the electrical load and charging the battery with power supplied from the external apparatus to the electronic apparatus, and a second control unit that controls the second switch unit based on whether power is supplied from the external apparatus to the electronic apparatus. In a case where power is not supplied from the external apparatus to the electronic apparatus, the second control unit controls the second switch unit to supply power from the battery to the electrical load via the second switch unit.

Abstract: A latch circuit includes a first input node, a second input node, a first output node, a second output node, a first switching device coupled between the first output node and the second output node, and a first amplification circuit coupled with the first input node, the second input node, the first output node, and the second output node. The first switching device is configured to be turned on in response to a first state of a clock signal and to be turned off in response to a second state of the clock signal. The first amplification circuit is configured to cause a voltage difference across the first switching device based on voltage levels of the first input node and the second input node in response to the first state of the clock signal.

Abstract: A semiconductor apparatus includes a detection voltage generation circuit configured to generate a first detection voltage and a second detection voltage of which voltage levels are varied according to characteristics of a PMOS transistor and an NMOS transistor in response to a detection enable signal, a code generation circuit configured to generate a detection code in response to the voltage levels of the first and second detection voltages, a reference voltage generation circuit configured to generate a reference voltage in response to the detection code, an internal voltage generation circuit configured to generate an internal voltage in response to the reference voltage, and an internal circuit configured to operate by receiving the internal voltage.

Abstract: A system includes a controller programmed to control an inverter to supply a power grid with a maximum amount AC electrical power while operating within an operating area that is pre-defined based on hardware limitations of the inverter. The system allows the inverter to operate with a variable low-DC voltage input into the inverter as opposed to a preset threshold DC voltage, thereby maximizing the amount of power the inverter supplies to a power grid. The inverter controller operates by prioritizing the reactive power output by the inverter over the active power output by the inverter so that the inverter is able to generate an output that meets the reactive power command from a utility and supplies the maximum amount of active power.

Abstract: The fault ride-through and power smoothing system includes a buck converter for Maximum Power Point Tracking (MPPT) of a PV array power system, a buck-boost converter to connect a supercapacitor energy storage system (SCESS) to the DC link, and a voltage source converter (VSC) to transfer the DC link power to the grid. Three independent controllers are implemented, one for each power electronics block. The effectiveness of the controllers is examined on Real Time Digital Simulator (RTDS).

Abstract: Duty cycle sampling circuitry is disclosed that may generate offsets that cancel each other out, thereby improving the accuracy of duty cycle sampling of input clock signals based on sampling clock signals. The input clock input signals may be swapped, or the sampling clock signals may be swapped, or both may be swapped, at various times. Erroneous samples obtained in one configuration can cancel out other erroneous samples obtained in another configuration.

Abstract: A switch actuation detection unit has a switch actuation voltage reception terminal and a logic circuit. The logic circuit includes a first port, a second port, a zener diode, and a signal port. The switch actuation voltage reception terminal receives a switch actuation voltage. The first port is connected to the switch actuation voltage reception terminal. A first terminal of the zener diode is connected to the switch actuation voltage reception terminal while a second terminal of the zener diode is connected to the second port. The signal port provides a plurality of pre-determined switch state signals.

Abstract: In one embodiment, a (pre)driver circuit includes first and a second output terminal for driving an electronic switch that includes a control terminal and a current path through the switch. The arrangement can operate in one or more first driving configurations (e.g., for PMOS), with the first and second output terminals are coupled to the current path and the control electrode of the electronic switch, respectively, and one or more second driving configurations (e.g., for NMOS, both HS and LS), wherein the first and second output terminals of the driver circuit are coupled to the control electrode and the current path of the electronic switch, respectively.

Abstract: A power transfer system and method are provided for transferring power from an AC supply outputting a first AC voltage. The system includes a controller and a matrix converter coupled to the AC supply for converting the first AC voltage to a second AC voltage. A primary coil is connected to the matrix converter and a secondary coil is in communication with the primary coil for producing an induced AC voltage. A secondary rectifier is connected to the secondary coil for rectifying the induced AC voltage to produce a secondary DC voltage. A sensor is coupled to the secondary rectifier and to the controller for monitoring the secondary DC voltage and outputting a proportional signal. The controller is configured to control the matrix converter producing a desired second AC voltage at a desired operating frequency and maintain a predetermined secondary DC voltage in response to the signal from the sensor.

Abstract: A Schmitt trigger circuit includes a first inverter, second inverter, first feedback unit, and second feedback unit. The first inverter includes a PMOS transistor unit and an NMOS transistor unit which generate an internal signal by inverting an input signal based on a first feedback signal and provide the internal signal to a first node. A second inverter generates an output signal by inverting the first signal. A first feedback unit generates a first feedback signal providing a first hysteresis character to a first unit among the PMOS transistor unit and NMOS transistor unit based on a first signal of the first node. A second feedback unit generates a second feedback signal providing a second hysteresis character to a second unit among the PMOS transistor unit and NMOS transistor unit based on the output signal. The second feedback unit provides the second feedback signal to the first node.

Abstract: A multi-output power management method used in a UPS system for enabling a microcontroller to determine whether to execute an automatic setting or manual setting. In automatic setting, the microcontroller conducts the parameter setting of a multi-output selector output mode, and switches a multi-output selector to a bypass or DC to AC inverter output mode after confirming that the power status parameter is in a predetermined multi-output selector parameter setting range. In manual setting, the multi-output selector can be manually switched to the bypass or DC to AC inverter output mode. Thus, multiple switching units of the multi-output selector of the UPS system can be respectively selectively switched to the bypass or DC to AC inverter output mode to provide different AC outputs to a respective load under the priority of energy saving or electrical safety, enhancing the electrical efficiency of UPS system and achieving the effect of energy saving.

Abstract: A method for driving a load includes driving a load to an initial voltage within a voltage window, the voltage window based on an input voltage and an offset voltage, and driving the load to approximately the input voltage.

Abstract: Power controller includes a switching circuit that is configured to provide electrical power to a load. The switching circuit includes a first path having a first switch and a second path that is in parallel with the first path prior to the load. The second path includes a second switch. The switching circuit is in a soft-switching state when the second path is activated and the first path is deactivated. The switching circuit is in an operational state when the second path is deactivated and the first path is activated. The power controller includes a processing unit that is configured to open or close the first and second switches to change the switching circuit between the soft-switching state and the operational state.

Abstract: Aspects of the disclosure are directed to communications between respective power domains (circuitry) that may operate in a stacked arrangement in which the each domain operates over a different voltage range. A first circuit provides differential outputs that vary between first and second voltage levels, based on transitions of an input signal received from a first one of the power domains. First and second driver circuits are respectively coupled to the first and second differential outputs. A third driver circuit operates with the first and second circuits to level-shift the input signal from the first power domain to an output signal on a second power domain by driving an output circuit at the second voltage level in response to the input signal being at the first voltage level, and driving the output circuit at a third voltage level in response to the input signal being at the second voltage level.

Abstract: A system for recognizing and swapping polarity for DC powered devices that includes a polarity detection module that is configured to identify polarity of DC power input, and further configured to send an output to a controller based on identification of polarity of the DC power input. The system includes a power switch array that is operatively coupled with the controller, and wherein the controller, based on the output, can set one or more switches of the power switch array for executing polarity switching.

Abstract: A buffer circuit includes a first capacitor having a first terminal coupled to receive an input signal, a second capacitor having a first terminal coupled to the first terminal of the first capacitor, and a latching portion coupled to a second terminal of the first capacitor and a second terminal of the second capacitor. The latching portion provides an output signal. A first transistor includes a control electrode coupled to receive the output signal, a first current electrode coupled to a first bias voltage supply terminal, and a second current electrode coupled to the second terminal of the second capacitor.

Abstract: Provided is a power amplification module that includes: a first power amplifier that amplifies a first signal and outputs a second signal; and a first noise removing circuit that is inputted with a first voltage supplied from a DC-DC converter, removes noise from the first voltage in order to generate a second voltage, and outputs the second voltage as a power supply voltage of the first power amplifier.

Abstract: A circuit including: a plurality of first switches connected in parallel between a first terminal and a second terminal; and a control circuit capable of implementing the following steps at each period of a clock signal: comparing the voltage between the first and second terminals with a reference voltage; if the voltage between the first and second terminals is greater than the reference voltage, turning on one of the first switches without modifying the state of the other switches; and if the voltage between the first and second terminals is smaller than the reference voltage, turning off one of the first switches without modifying the state of the other switches.