Abstract: A level shifter circuit is disclosed. A level shifter circuit includes a static pull-down circuit that causes an output node to be pulled low responsive to an input circuit receiving a first logic value on an input node. The input node is coupled to receive a signal from circuitry in a first voltage domain, while the output node is configured to provide a corresponding signal into a second voltage domain. The static pull-down circuit is implemented with a passgate having a pair of transistors coupled in series. The level shifter circuit further includes a dynamic pull-up circuit that, when active, causes the output node to be pulled high responsive to the input circuit receiving a second logic value on the input node. The dynamic pull-up circuit includes third and fourth transistors coupled in series between the output node and a supply voltage node of the second voltage domain.

Abstract: A device voltage shifter includes a first voltage reference node, a second voltage reference node, an output node and a clamp node. A first high-voltage switching transistor of the voltage shifter has a first conduction terminal coupled to the first voltage reference node and a second conduction terminal coupled to the clamp node. A second high-voltage switching transistor of the voltage shifter has a first conduction terminal coupled to the clamp node and a second conduction terminal coupled to the second voltage reference node. A third high-voltage switching transistor of the voltage shifter has a first conduction terminal coupled to the first voltage reference node, a control terminal coupled to the clamp node, and a second conduction terminal coupled to the output node. A voltage regulator of the voltage shifter is coupled between the output node and the clamp node.

Abstract: In described examples, an apparatus includes: a counter configured to receive a reference clock signal and having a next state input and a current state output; a multiplexer coupled to the next state input of the counter, configured to output one of an incremented next state value and a corrected next state count value responsive to a count correction select control signal; a seconds reference circuit coupled to the current state output of the counter, configured to output a seconds reference signal; an incrementer coupled to the current state output of the counter, configured to output the incremented next state value; and a calibration compensation circuit coupled to a compensate up down input signal and to the current state output of the counter, configured to output the corrected next state count value and the count correction select control signal.

Abstract: There is provided a power supply system including a first power supply and a second power supply. The power supply system includes a power conversion circuit capable of bidirectionally sending and receiving power by bidirectional voltage conversion between the first power supply and the second power supply, converting the first voltage from the first power supply to output a third voltage and a fourth voltage, and converting the second voltage from the second power supply to output the third voltage and the fourth voltage.

Abstract: A non-contact type power transmitting apparatus may include a rectifying unit rectifying alternating current (AC) power, a power converting unit converting the power rectified by the rectifying unit into direct current (DC) power through a single power converting operation and switching and transmitting the DC power, and a power transmitting coil transmitting transmission power transmitted from the power converting unit externally in a non-contact scheme.

Abstract: Disclosed is a voltage regulating circuit, comprising an input end, an output end, a protecting switch, a first switch, a second switch, a third switch, a first coil and a second coil. The third switch comprises a first terminal and a second terminal. The second terminal of the third switch is connected to a third terminal of the first switch. One end of the first coil is connected to a second terminal of the first switch, and the other end of the first coil is connected to a third terminal of the first switch. One end of the second coil is connected to a first terminal of the third switch, and the other end of the second coil is connected to a fourth terminal of the protecting switch. Different connections between switches and the transformer provide various voltage adjustments to reduce power loss and to increase power transformation efficiency.

Abstract: A level shifting circuit includes an input circuit, a leakage divider circuit, a skew inverter circuit and a buffering circuit. The input circuit has an input terminal configured to receive an input voltage. The input circuit is configured to receive a first voltage and a second voltage. The leakage divider circuit is configured to receive a third voltage. The leakage divider circuit is connected to the input circuit. The skew inverter circuit is configured to receive the third voltage. The skew inverter circuit is connected to the leakage divider circuit and the input circuit. The buffering circuit has a terminal configured to output an output voltage. The buffering circuit is connected to an output terminal of the skew inverter circuit. The level shifting circuit is free of capacitors.

Abstract: A system and method for operating one or more light emitting devices is disclosed. In one example, the intensity of light provided by the one or more light emitting devices is adjusted responsive to current feedback from the one or more light emitting devices.

Abstract: A power supply system includes: a power supply terminal, for receiving first power from an external power source or outputting second power to a load; at least one battery, for receiving and storing first power in a charging mode, and outputting second power to the power supply terminal in a discharging mode; a charger, enabled in the charging mode for charging the battery by first power; a switch, turned on in the discharging mode for transmitting second power to the power supply terminal; a current detection circuit, for detecting a current of the power supply terminal to determine whether the power supply system is operated in the charging or discharging mode. The current detection circuit controls the charger to be enabled in the charging mode and disabled in the discharging mode, and controls the switch to be turned on in the discharging mode and turned off in the charging mode.

Abstract: A circuit includes a biasing circuit that includes a diode stack coupled to a first node. The biasing circuit can output a biasing signal on the first node. The biasing circuit also includes a transistor, a timer component and a current source. An input of the timer component is coupled to receive an isolation signal. The current source is configured to inject current for a period of time into the diode stack in response to a transition of the ISO signal between a first voltage and a second voltage. The biasing circuit also is configured to output a signal to a level shifter to hold an output of the level shifter in a known state for a specified amount of time after power-up of the circuit for proper operation of the level shifter.

Abstract: An exemplary control apparatus for an energy distribution system includes a connection to an alternating current supply system and a plurality of predetermined loads each having an energy storage capacity and being electrically connected as by a respective switching device to the alternating current supply system for a duration of a half-wave or a whole number times said half-wave. The respective switching devices are supplied electrical energy from the alternating current supply system for a respective control time period within a predetermined common cycle time period. The start and end of the respective control time periods within the common cycle time period are established prior to the start of said common cycle time period to create a substantially constant loading graph. The optimization procedure is based at least one load in lieu of a continuous control time period having at least two non-continuous block time periods of equal total duration.

Abstract: A latch circuit providing isolated input current paths includes a pair of input transistors that receive a differential input signal. A plurality of steering transistors receive a portion of a differential clock signal. The latch circuit includes a positive output node and a negative output node. A first bypass input current path is associated with the first input transistor and is electrically isolated from the positive output node and the negative output node. A second bypass input current path associated with the second input transistor is also electrically isolated from the positive output node and the negative output node. In a latched state, the clock signal is operative to selectively bias the plurality of steering transistors such that current is steered to one of the first input current path or the second input current path, thereby being isolated from the output nodes.

Abstract: Systems and methods disclosed herein provide for a fractional feedback divider with reduced jitter at the output without increasing the input clock frequency and with minimal power increase. Embodiments of the system provide for interpolating, with a multiplexer, different output clock signals depending on whether an extra half period of resolution from the input clock is needed for a certain output clock cycle.

Abstract: A switchable uninterruptible power supply (SUPS) system is provided. The system includes a UPS configured to supply power to a load, a plurality of battery units connected in parallel, and a controller configured to selectively supply power from a grid to the UPS and to selectively connect each of the plurality of battery units the UPS or a battery charger are connected to the grid.

Abstract: Systems and methods associated with phase frequency detection are disclosed. In one illustrative implementation, a phase frequency detection (PFD) circuit device may comprise first circuitry and second circuitry having a set input, a reset input, and an output, wherein the set input has a higher priority than the reset input, and additional circuitry arranged and operatively coupled to provide advantageous operation of the PFD circuit device. According to some implementations, for example, systems and methods with clock edge overriding reset features, extended detection range(s), and/or reduction of reverse charge after cycle slipping are provided.

Abstract: An external power supply and a system connection detection unit applied thereto are provided. For providing DC power, the external power supply separably connects with a positive input terminal and a negative input terminal of a system through a positive output terminal and a negative output terminal respectively. When the positive output terminal and the negative output terminal are respectively connected to the positive input terminal and the negative input terminal, a system detection terminal connects with a system connection terminal of the system, and a connection status signal generated by the system connection detection unit switches the operation of the external power supply from a deep sleeping mode to a normal operation mode. The system connection terminal is electrically connected to one of the positive input terminal and the negative input terminal through at least a first resistive element.

Abstract: A buffer includes an amplification circuit, an amplification current generation circuit, and a latch. The amplification circuit may change voltage levels of a first output node and a second output node based on a clock signal and a pair of input signals. The amplification current generation circuit may provide currents having different magnitudes to the first and second output nodes during a first operation period, and may provide currents having the same magnitude to the first and second output nodes during a second operation period. The latch circuit may latch the voltage levels of the first output node and the second output node based on the clock signal.

Abstract: An uninterruptible power supply (UPS) system for preventing charging of batteries is provided. The system includes a UPS configured to supply power from a grid to a load, a battery unit configured to be charged with the power supplied from the UPS, and a controller configured to selectively supply the power from the grid to the UPS and selectively connect or disconnect a charging path between the UPS and the battery unit.

Abstract: Aspects of the present disclosure are directed to methods, apparatuses and systems involving voltage control using rectifying circuitry. According to an example embodiment, an apparatus includes an antenna, a capacitor, and voltage control circuitry. The voltage control circuitry includes a first rectifying circuit to rectify a wireless signal and provide the rectified signal to an output load, a second rectifying circuit to rectify the wireless signal and provide the rectified signal to the capacitor, and a control logic circuit to regulate an output voltage provided to the output load relative to a threshold value. For each rectifying cycle, the control logic circuit determines whether the output voltage is above the threshold value, enables, in response to determining that the output voltage is below the threshold value, the first rectifying circuit, and enables, in response to determining that the output voltage is above the threshold value, the second rectifying circuit.

Abstract: A semiconductor circuit includes a first circuit determining a voltage of a first node in response to the clock signal and the input data signal, a first latch determining a voltage of a second node in response to the clock signal and the voltage of the first node, and a second circuit determining a voltage of a third node in response to the clock signal and the voltage of the second node. The output data signal is provided in response to the voltage of the third node, the clock signal controls a flip-flop operation with respect to the input data signal and the output data signal, and respective voltages are maintained constant at the first node, second node and third node regardless of level transitions in the clock signal so long as a level of the input data signal is maintained constant.