Abstract: A data processor for latching in a floating point register floating point data having exponent parts of fixed and variable lengths, which are transferred from a main storage or an arithmetic unit as they are, but are not converted to another data expression type. When the data of the two representation types are to be input for computations from the floating point register or storage to the arithmetic unit, there is provided circuitry for controlling the data to be computed after that data has been converted into data having an exponent part of fixed length representation, in the arithmetic case of data having an exponent part of the variable length representation, and data to be computed without any data conversion in the arithmetic case of data having an exponent part of the fixed length representation. By thus controlling the two computations discriminatively, it is possible to realize the processing time periods matching the respective data widths.

Abstract: The digital interpolator herein selectively provides linear interpolation between successive digital data words in a stream of such data words. The data words each contain a control bit together with first and second multi-bit fields with the control bit having a first or second level respectively designating whether or not interpolation is to take place through that data word. The first bit field contains differential data, representing the value between successive data words, only when the control bit is at a first level. The second bit field contains the interpolation interval to be effective when the control bit is at the second level. When no interpolation through the assigned data point is desired, the control bit is at the first level and the circuitry responds to provide an output signal having a digital value corresponding with a first data word to which there is added the differential data from the first bit field to obtain the next output signal.

Abstract: A high-speed dividing apparatus includes a first, second and third carry save adders (CSA's) and the outputs of the first CSA are connected to the inputs of the second and third CSA's. The first CSA is capable of carrying out either the addition or the subtraction of a divisor. The second CSA is adapted to carry out the subtraction of a divisor, and the third CSA the addition thereof. A carry look-ahead logic is connected to each CSA. A quotient determining logic is adapted to determine quotient bits in response to outputs from CSA's and carry look-ahead logics. A selector control logic is adapted to control selectors in response to quotient bits so that outputs from one of the second and third CSA's and either a divisor or the complement thereof are selectively supplied to the inputs of the first CSA. An arbitrary number of stages can be arranged in a binary tree configuration in the same manner.

Abstract: An arithmetic logic system for performing a variety of arithmetic and logical functions on pixel input streams such as averaging down the input image stream, computation of absolute values, and signed or unsigned, clipped or unclipped, addition, subtraction and multiplication. The arithmetic logic system has a first arithmetic logic unit connected to a plurality of input signals. A second arithmetic logic unit is coupled to the first arithmetic logic unit and operates on the output of the first arithmetic logic unit. A control unit is coupled to the first and second arithmetic logic units and controls the operation of the second arithmetic logic unit based on the output of the first arithmetic logic unit.

Abstract: An arithmetic logic unit capable of performing AND, OR, exclusive-OR, and add functions is implemented utilizing strobed gates. An input section receives first and second inputs, each capable of assuming first and second states, and generates a first output indicating that at least one of the inputs is in a first state and a second output indicating that both inputs are in the first state. First, second and third strings of field-effect-transistors controlled by a plurality of control signals are selectively enabled respectively when at least one of the inputs is in the first state, all of the inputs are in the first state, or when only one of the inputs is in the first state. The circuit includes an output section and a circuit for generating a carry-out signal when the inputs so require.

Abstract: A compact rectangular parallel multiplier array of Booth summation cells includes along a left edge a cell which reduces to two the number of sign-extension bits sufficient to generate subsequent intermediate products. The cell employs optimized logic circuitry which generates a sum, a carry and a guard bit for use during generation of the next most-significant intermediate product.

Abstract: An angle modulated periodic waveform is synthesized by generating three digital number sequences. In a first number sequence, one number thereof is generated on each occurrence of a periodic clock signal and has a magnitude which is a selected first periodic function of the number of prior occurring clock signals. In a second number sequence, one number thereof is generated on each occurrence of the clock signal and has a magnitude which is a selected second function of prior occurring numbers of the first number sequence and an applied constant carrier waveform frequency parameter. Each number of the second number sequence is added as it is generated to a stored second address number. In the third number sequence, one number thereof is generated on each occurrence of the clock signal and has a magnitude which is a selected third periodic function of the stored second address number.

Abstract: A portable computer is sized to fit into a businessman's attache case and may be seated on a surface for use in either a normal position or a tilted forward position. The portable computer includes a housing having a base, a front top cover, a rear top cover and a foot door. The front top cover is pivotally attached to the front of the rear top cover and the rear top cover is fixedly attached to the base. Computer electronics (i.e. printed circuit boards), and two floppy disk drives are mounted inside the housing on the base at the rear and a full size keyboard is mounted inside the housing on the base at the front. A battery pack is disposed in the rear top cover of the housing. A full size liquid crystal display monitor is mounted on the front top cover. The foot door is movably mounted on the back of the base. When the front top cover is pivoted open the display screen is viewable and the keyboard is accessible.

Abstract: Memory 60 contains a decision table which is a replica of the particular N-bit pattern to be detected. When a bit is received over line 12, a table lookup operation is performed to determine whether the entry at the address indicated by address counter 34 contains a bit that matches the received bit. If so, the content of the address counter is incremented by one and the device waits for another bit to be received over line 12. If the bit in the entry does not match the received bit, then, if the address indicated by the counter is zero, the count of the counter is maintained at zero and the device waits for another bit to be received; or, if the address is different from zero, the counter is reset to zero and the bit present on line 12 is again presented to the table in order, this time, to be compared with the bit in the entry at address zero. The pattern is detected when the address contained in the counter is equal to N and when the last bit in the pattern matches the bit with which it is compared.

Abstract: A logic circuit incorporating carry look-ahead in which efficiency can be achieved regarding the hardware for generating the sum signals and carry signals by a suitable choice of the adder gate, making use of the already present signal a.sub.1 .multidot.b.sub.i which is used for generating the carry look-ahead signal.

Abstract: Apparatus for comparing a stream of data characters with a predetermined string of test characters has an input device for receiving the stream of data characters and a main processor for generating the predetermined string of test characters. A hardware register receives the predetermined string of test characters from the main processor, and a comparator device compares the stream of data characters with the contents of the register device and generates a response in the event that a portion of the stream is identical to the string of test characters generated by the main processor. A second processor receives the response and sends a report to the main processor.

Abstract: Digital computation is performed on an integrated optical circuit level using optical threshold logic elements. Each input and output optical beam of each element occupies a separate channel and interacts with only one switching component thus assuring true digital computation. These circuits provide access to the entire class of logic functions routinely utilized in electronic digital computers. The integrated optical devices are programmable and are capable of high speed logic operations and reliable digital operation in a complex network.

Abstract: A method and apparatus for radix-.beta. non-restoring division. The division process occurs in four phases. In a first phase, the input operands are transformed to produce a divisor lying in a designated numerical range. Next, a transitional phase involves generating an initial radix-.beta. quotient digit from the transformed numerator. An iterative phase of the process generates successive partial remainders according to a recursive method. From the sign and a single radix-.beta. digit of each of these partial remainders, the process generates a radix-.beta. quotient digit. Further, a fourth phase, which may run concurrently with the transitional and iterative phases, involves accumulating successively generated quotient digits to produce a final quotient value.

Abstract: A hybrid arithmetic processor which combines attributes of conventional floating point (F.P) arithmetic with logarithmic number system (LNS) arithmetic. The arithmetic processor includes an input section (forward code converter) for converting input operands in F.P. format to intermediate operands in LNS format, an LNS arithmetic section for performing an arithmetic operation on the LNS intermediate operands and providing an intermediate output in LNS format, and an output section (inverse code converter) for converting the LNS intermediate output to an output in F.P. format. Significantly, output is provided in normalized floating point format but without the need for a time-consuming exponent alignment operation. Arithmetic operations, including addition and multiplication, are accomplished at a high speed, which speed moreover is constant and independent of the data. An efficient accumulator structure and the structure of an ultra-fast numeric processor are disclosed.

Abstract: Apparatus and method for performing a mathematical operation, e.g., addition on two signals composed of a string of n digits or bits in a number system having a predetermined base wherein A.sub.i and B.sub.i represents each digit in the respective strings and with i being the specific column or bit number from 0 to n. The mathematic operation is performed by first circuitry on the A.sub.i and B.sub.i digits without reference to the results of that operation of any other column or bit number. Substrings of the B string are compared by second circuitry to corresponding substrings of C string which for addition is the base minus one complement of the A string. Third circuitry are provided responsive to the first and second circuitry to produce a resultant output signal composed of at least n digits representing the results of the mathematic operation.

Abstract: A device for computing interpolated values of a waveform generated in an electronic device, includes a memory for storing waveform data of a periodic sinusoidal wave, and an address signal generator for generating an address signal. The waveform data consists of sine wave data and cosine wave data. An address signal from the generator or a signal obtained by inverting the address signal (i.e., inverted address signal) is supplied to the memory. Upon receipt of the address signal, the memory reads out the sine wave data or the cosine wave data. Upon receipt of the inverted address signal, it reads out the remaining wave data. The wave data read from the memory is multiplied by a multiplier, which produced an interpolated value. An adder adds this value to the sine or consine wave data read out from the memory when the inverted address signal is supplied to the memory, and computes amplitude value data corresponding to the address signal.

Abstract: A calculator for use by teachers for rapidly and easily converting numeric scores into letter grades. The calculator includes a memory device for storing a user-defined set of numeric score ranges and the letter grades corresponding thereto. As individual student numeric scores are inputted, the calculator determines the range within which each numeric score lies and the letter grade corresponding thereto. In a preferred aspect, the score ranges are selectable by the user. In another preferred aspect, grade points are also calculated for the student numeric scores.

Abstract: A set value of a frequency setting register is accumulated upon each occurrence of a clock signal, and a waveform memory is read out by using the accumulated value as an address. In the waveform memory, amplitude data of one cycle of the waveform of a burst signal to be generated are stored at fixed phase intervals. The output read out of the waveform memory is converted into an analog signal. A wave-number counter counts the number of times the amplitude data of one cycle is read out of the waveform memory and, when having counted by a preset number of waves, yields a wave-number counting end signal. After the occurrence of the wave-number counting end signal, a phase counter counts clock signals, and, when the count value of the phase counter reaches a value corresponding to a preset end phase, the generation of the burst signal is stopped.

Abstract: An enhancement to a typical four-function calculator. With this enhanced calculator, lottery players may generate psuedo-random integer combinations for their use in selecting numbers on which to place their bets. The enhanced calculator allows users to select the type of lottery game for which the number combinations will be generated by specifying the quantity of numbers generated and the bounds of the range within which the numbers will be generated through two key strokes of dedicated keys. The first key stroke utilizes a key designated by the particular lottery game. The second key stroke utilizes a key designated by a popular range of numbers used by the various lotteries. This invention relieves the user from having to rely on his limited supply of "magical" dates, ages, social security numbers and so forth.

Abstract: A digital multiplying circuit in a parallel multiplying circuit which can multiply an input which changes at a high data rate by the pipeline processing. A multiplicand is inputted to this circuit. Partial product signal generating circuits of the number corresponding to only the number of partial product signals which are needed are provided. The partial product signal generating circuits produce the partial product signals in accordance with the state of predetermined bits of a multiplier. Each partial product signal is added, thereby obtaining a multiplication output of the multiplicand. The pipeline processing is performed in the adding operation of each partial product signal. The multiplier and multiplicand are delayed. The predetermined partial product signal generating circuits are arranged immediately before the adders which need the partial product signals, thereby obtaining the partial product.