Abstract: An organic light emitting display apparatus and a method of manufacturing the same wherein in the organic light emitting device, each of the first to third sub pixels includes: a thin film transistor; a pixel electrode electrically connected to the thin film transistor; and an organic light emitting layer electrically connected to the pixel electrode; and an opposite electrode formed on each of the organic light emitting layers. A pad part is disposed on the non-display region, the pad part including at least one side exposed. The first sub pixel includes a first transmissive conductive layer and a second transmissive conductive layer sequentially stacked between the pixel electrode of the first sub pixel and the organic light emitting layer. The second sub pixel includes the first transmissive conductive layer between the pixel electrode of the first sub pixel and the organic light emitting layer.

Abstract: A package for a semiconductor die includes a die attach pad that provides an attachment surface area for the semiconductor die, and tie bars connected to the die attach pad. The die attach pad is disposed in a first general plane and the tie bars are disposed in a second general plane offset with respect to the first general plane. A molding compound encapsulates the semiconductor die in a form having first, second, third and fourth lateral sides, a top and a bottom. The tie bars are exposed substantially coincident with at least one of the lateral sides. The form includes a discontinuity that extends along the at least one of the lateral sides, the discontinuity increasing a creepage distance measured from the tie bars to the bottom of the package.

Abstract: According to one embodiment of a module, the module includes a plurality of gate driver chips coupled in parallel and having a common gate input, a common supply voltage and a common output. The chips are spaced apart from one another and have a combined width extending between an edge of a first outer one of the chips and an opposing edge of a second outer one of the chips. The module further includes a plurality of capacitors coupled in parallel between ground and the common supply voltage, and a transverse electromagnetic (TEM) transmission line medium coupled to the common output of the chips and having a current flow direction perpendicular to the combined width of the chips.

Abstract: Systems and methods of fabricating Wafer Level Chip Scale Packaging (WLCSP) devices with transistors having source, drain and gate contacts on one side of the transistor while still having excellent electrical performance with low drain-to-source resistance RDS(on) include using a two-metal drain contact technique. The RDS(on) is further improved by using a through-silicon-via (TSV) technique to form a drain contact or by using a copper layer closely connected to the drain drift.

Abstract: A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected amount so as to achieve a desirable coupling between the substrate, the floating gate and the control gate comprising the flash cell.

Abstract: A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device.

Abstract: An optoelectronic component with a semiconductor body includes an active region suitable for generating radiation, and two electrical contacts arranged on the semiconductor body. The contacts are electrically connected to the active region. The contacts each have a connecting face that faces away from the semiconductor body. The contact faces are located on a connection side of the component and a side of the component that is different from the connection side is mirror-coated. A method for the manufacture of multiple components of this sort is also disclosed.

Abstract: A spin wave device comprises a metal layer, a pinned layer, a nonmagnetic layer, a free layer, an antiferromagnetic layer, a first electrode, a first insulator layer, and a second electrode. The pinned layer has a magnetization whose direction is fixed. The free layer has a magnetization whose direction is variable.

Abstract: A first low dielectric constant (low-k) dielectric material layer is lithographically patterned to form a recessed region having expose substantially vertical sidewalls, which are subsequently damaged to de-carbonize a surface portion at the sidewalls having a sublithographic width. A second low-k dielectric material layer is deposited to fill the recessed region and planarized to exposed top surfaces of the damaged low-k dielectric material portion. The damaged low-k dielectric material portion is removed selective to the first and second low-k dielectric material layers to form a trench with a sublithographic width. A portion of the pattern of the sublithographic-width trench is transferred into a metallic layer and optionally to an underlying dielectric masking material layer to define a trench with a sublithographic width, which can be employed as a template to confine the widths of via holes and line trenches to be subsequently formed in an interconnect-level dielectric material layer.

Abstract: According to one embodiment, a semiconductor device includes a channel formation region of first conductivity type, a first offset region of second conductivity type, a first insulating region, a first liner layer, a first semiconductor region of second conductivity type, a second semiconductor region of second conductivity type, a gate insulating film, and a gate electrode. The first liner layer is provided between the first offset region and the first insulating region. The first semiconductor region of second conductivity type is provided on the side opposite to the channel formation region sandwiching the first insulating region therebetween and having impurity concentration higher than that of the first offset region. The second semiconductor region of second conductivity type is provided on the side opposite to the first semiconductor region sandwiching the channel formation region therebetween and having impurity concentration higher than that of the first offset region.

Abstract: The present invention relates to a semiconductor device and a semiconductor package having the same. The semiconductor device includes a conductive element. The conductive element is disposed on a protruded conductive via and liner, and covers a sidewall of the liner. Whereby, the conductive element can protect the protruded conductive via and liner from being damaged. Further, the size of the conductive element is large, thus it is easy to perform a probe test process.

Abstract: An organic light-emitting display device and a method of manufacturing the same. The organic light-emitting display device includes a first film formed of an inorganic material, a second film that is formed of an organic material and formed on the first film, and includes a first surface and a second surface facing each other and lateral surfaces at boundaries of the first surface and the second surface, with the first surface contacting the first film, a third film that is formed of an inorganic material and covers the second surface and lateral surfaces of the second film, with a first sealing region contacting the first film being formed at a boundary between the second film and the third film, an organic light-emitting unit that is disposed on the third film to overlap with the second film, and a fourth film that covers the organic light-emitting unit, with a second sealing region contacting the third film being formed at a boundary of the fourth film.

Abstract: Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations are defined on a layered semiconductor wafer. The layered semiconductor wafer preferably includes a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). Portions of the buried layer are converted to dielectric material, e.g., Aluminum Oxide (AlO), at least beneath FET source/drain regions. The converted dielectric material may extend completely under the FET. Source/drain contacts are formed to FETs above the dielectric material in the buried layer.

Abstract: The present invention can realize a highly-integrated semiconductor device having a MONOS type nonvolatile memory cell equipped with a split gate structure without deteriorating the reliability of the device. A memory gate electrode of a memory nMIS has a height greater by from 20 to 100 nm than that of a select gate electrode of a select nMIS so that the width of a sidewall formed over one (side surface on the side of a source region) of the side surfaces of the memory gate electrode is adjusted to a width necessary for achieving desired disturb characteristics. In addition, a gate electrode of a peripheral second nMIS has a height not greater than the height of a select gate electrode of a select nMIS to reduce the width of a sidewall formed over the side surface of the gate electrode of the peripheral second nMIS so that a shared contact hole is prevented from being filled with the sidewall.

Abstract: A method for manufacturing a micromechanical sound transducer includes depositing successive layers of first and second membrane support material on a first main surface of a substrate arrangement with a first etching rate and a lower second etching rate, respectively. A layer of membrane material is then deposited. A cavity is created in the substrate arrangement from a side of the substrate arrangement opposite to the membrane support materials and the membrane material at least until the cavity extends to the layer of first membrane support material. The layers of first and second membrane support material are etched by applying an etching agent through the cavity in at least one first region located in an extension of the cavity also in a second region surrounding the first region. The etching creates a tapered surface on the layer of second membrane support material in the second region.

Abstract: A method of implementing bandgap tuning of a graphene-based switching device includes subjecting a bi-layer graphene to an electric field while simultaneously subjecting the bi-layer graphene to an applied strain that reduces an interlayer spacing between the bi-layer graphene, thereby creating a bandgap in the bi-layer graphene.

Abstract: An organic thin film transistor comprising: a substrate; a source electrode and a drain electrode defining a channel; a layer of insulating material disposed over the source and drain electrodes; a layer of organic semi-conductive material extending across the channel; a layer of dielectric material; and a gate electrode disposed over the layer of dielectric material.

Abstract: An oxide semiconductor thin film transistor includes a gate electrode on a substrate, the gate electrode having a first area, a gate insulation layer on the gate electrode, the gate insulation layer covering the gate electrode, an active layer on the gate insulation layer, the active layer having a second area that is smaller than the first area, a source electrode on the active layer, the source electrode contacting a source region of the active layer, a drain electrode on the active layer, the drain electrode contacting a drain region of the active layer, and a passivation layer covering the active layer, the source electrode, and the drain electrode.

Abstract: A method of implementing bandgap tuning of a graphene-based switching device includes subjecting a bi-layer graphene to an electric field while simultaneously subjecting the bi-layer graphene to an applied strain that reduces an interlayer spacing between the bi-layer graphene, thereby creating a bandgap in the bi-layer graphene.

Abstract: Generally, the subject matter disclosed herein relates to sophisticated semiconductor chips that may be less susceptible to the occurrence of white bumps during semiconductor chip packaging operations, such as flip-chip or 3D-chip assembly, and the like. One illustrative semiconductor chip disclosed herein includes, among other things, a bond pad and a metallization layer below the bond pad, wherein the metallization layer is made up of a bond pad area below the bond pad and a field area surrounding the bond pad area. Additionally, the semiconductor device also includes a plurality of device features in the metallization layer, wherein the plurality of device features has a first feature density in the bond pad area and a second feature density in the field area that is less than the first feature density.