Abstract: Generally, the subject matter disclosed herein relates to sophisticated semiconductor chips that may be less susceptible to the occurrence of white bumps during semiconductor chip packaging operations, such as flip-chip or 3D-chip assembly, and the like. One illustrative semiconductor chip disclosed herein includes, among other things, a bond pad and a metallization layer below the bond pad, wherein the metallization layer is made up of a bond pad area below the bond pad and a field area surrounding the bond pad area. Additionally, the semiconductor device also includes a plurality of device features in the metallization layer, wherein the plurality of device features has a first feature density in the bond pad area and a second feature density in the field area that is less than the first feature density.

Abstract: A fin transistor structure and a method of fabricating the same are disclosed. In one aspect the method comprises providing a bulk semiconductor substrate, patterning the semiconductor substrate to form a fin with it body directly tied to the semiconductor substrate, patterning the fin so that gaps are formed on the bottom of the fin at source/drain regions of the transistor structure to be formed. This is performed wherein a portion of the fin corresponding to the channel region of the transistor structure to be formed is directly tied to the semiconductor substrate, while other portions of the fin at the source/drain regions are separated from the surface of the semiconductor substrate by the gaps. Also, filling an insulation material into the gaps, and fabricating the transistor structure based on the semiconductor substrate with the fin formed thereon are disclosed. Thereby, it is possible to reduce the leakage current while maintaining the advantages of body-tied structures.

Abstract: A stacked structure of semiconductor packages includes an upper semiconductor package, a lower semiconductor package and inter-package connectors. The upper semiconductor package includes an upper package substrate, a plurality of upper semiconductor chips stacked on the upper package substrate, and conductive upper connection lands formed on a bottom surface of the upper package substrate. The lower semiconductor package includes a lower package substrate, a plurality of lower semiconductor chips stacked on the lower package substrate, and lower through-silicon vias vertically penetrating the lower semiconductor chips. The inter-package connectors may electrically connect the through-silicon vias to the upper connection lands.

Abstract: A semiconductor device includes a high-breakdown-voltage transistor having a semiconductor layer. The semiconductor layer has an element portion and a wiring portion. The element portion has a first wiring on a front side of the semiconductor layer and a backside electrode on a back side of the semiconductor layer. The element portion is configured as a vertical transistor that causes an electric current to flow in a thickness direction of the semiconductor layer between the first wiring and the backside electrode. The backside electrode is elongated to the wiring portion. The wiring portion has a second wiring on the front side of the semiconductor layer. The wiring portion and the backside electrode provide a pulling wire that allows the electric current to flow to the second wiring.

Abstract: Provided is a method of manufacturing a semiconductor device capable of adhering semiconductor elements and a support member for mounting semiconductor elements, such as lead frames, organic substrates or the like, even in a relatively low temperature range without damaging adhesion property and workability and of suppressing the occurrence of voids.

Abstract: In an SOI semiconductor device, substrate diodes may be formed on the basis of a superior design of the contact level and the metallization layer, thereby avoiding the presence of metal lines connecting to both diode electrodes in the critical substrate diode area. To this end, contact trenches may be provided so as to locally connect one type of diode electrodes within the contact level. Consequently, additional process steps for planarizing the surface topography upon forming the contact level may be avoided.

Abstract: An unattached, contained semiconductor device includes a semiconductor die, for example a MEMS pressure sensor die. The semiconductor die is unattached from the interior cavity of a surrounding containment body in that the semiconductor die is free of adherence to the containment body to mitigate packaging stress and strain between the containment body and the semiconductor die.

Abstract: In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package of the present invention includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include exposed bottom surface portions which are provided in at least two concentric rows or rings which at least partially circumvent the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads.

Abstract: The production of light of various wavelengths using IR phosphor down conversion techniques using existing LED emissions to pump sensitizer-rare earth ions that emit at other wavelengths. A sensitizer absorbs an LED chip pump emission and then transfers that energy with high quantum efficiency to dopant ions that then emits at their characteristic wavelength.

Abstract: A compound semiconductor device has a buffer layer formed on a conductive SiC substrate, an AlxGa1-xN layer formed on the buffer layer in which an impurity for reducing carrier concentration from an unintentionally doped donor impurity is added and in which the Al composition x is 0<x<1, a GaN-based carrier transit layer formed on the AlxGa1-xN layer, a carrier supply layer formed on the carrier transit layer, a source electrode and a drain electrode formed on the carrier supply layer, and a gate electrode formed on the carrier supply layer between the source electrode and the drain electrode. Therefore, a GaN-HEMT that is superior in device characteristics can be realized in the case of using a relatively less expensive conductive SiC substrate compared with a semi-insulating SiC substrate.

Abstract: A microphone assembly includes a microphone composed of a case having an open end and a printed circuit board. The printed circuit board is disposed in the open case end. The microphone assembly further includes a metal screen coupled to the case over the printed circuit board for shielding the microphone from electromagnetic interference. The metal screen includes several apertures.

Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

Abstract: Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar.

Abstract: A solid-state imaging device including an imaging area formed of a plurality of pixels arrayed in a two-dimensional matrix is provided. The solid-state imaging device includes: a photoelectric conversion portion including a charge accumulation region provided on a semiconductor substrate; a read transistor for reading electric charges from the photoelectric conversion portion; and a gettering site for separating metal impurities within the semiconductor substrate from at least the photoelectric conversion portion. The photoelectric conversion portion is provided on the surface side of the semiconductor substrate, and the gettering site is provided on the rear side away from the semiconductor substrate.

Abstract: A plasma torch includes a torch main unit and a nozzle. The torch main unit has a nozzle seat member on which the nozzle is mounted. The nozzle is arranged to move toward or away from the nozzle seat member in a direction substantially parallel to a center axis of the nozzle when the nozzle is mounted on or removed from the nozzle seat member. The nozzle has an electroconductive surface facing the nozzle seat member. The torch main unit has an elastic electric contact portion contacting with the electroconductive surface of the nozzle to form an electroconductive path for a pilot arc to the nozzle. The electroconductive surface of the nozzle presses the electric contact portion in the direction substantially parallel to the center axis when the nozzle is moved toward the nozzle seat member to mount the nozzle on the nozzle seat member.

Abstract: The present invention proposes a method of forming a dual contact plug, comprising steps of: forming a source/drain region and a sacrificed gate structure on a semiconductor substrate, the sacrificed gate structure including a sacrificed gate; depositing a first inter-layer dielectric layer; planarizing the first inter-layer dielectric layer to expose the sacrificed gate in the sacrificed gate structure; removing the sacrificed gate and depositing to form a metal gate; etching to form a first source/drain contact opening in the first inter-layer dielectric layer; sequentially depositing a liner and filling conductive metal in the first source/drain contact opening to form a first source/drain contact plug; depositing a second inter-layer dielectric layer on the first inter-layer dielectric layer; etching to form a second source/drain contact opening and a gate contact opening in the second inter-layer dielectric layer; and sequentially depositing a liner and filling conductive metal in the second source/drain

Abstract: A light emitting diode (LED) package includes a substrate and a light emitting diode (LED) die on the substrate configured to emit electromagnetic radiation in a first spectral region. The (LED) package also includes a dielectric layer on the (LED) die and a wavelength conversion member on the dielectric layer configured to convert the electromagnetic radiation in the first spectral region to electromagnetic radiation in a second spectral region. The (LED) package also includes an interconnect comprising a conductive trace on the wavelength conversion member and on the dielectric layer in electrical contact with a die contact on the (LED) die and with a conductor on the substrate, and a transparent dome configured as a lens encapsulating the (LED) die.

Abstract: Disclosed in a semiconductor device including a substrate, a first transistor, a second transistor, and a first source electrode and a first drain electrode of the first transistor are arranged along a first direction and a second source electrode and a second drain electrode of the second transistor are arranged in a reverse order of the first source electrode and the first drain electrode along the first direction, the first source electrode and the second source electrode are connected by a source connecting wiring, the first drain electrode and the second drain electrode are connected by a drain connecting wiring, a first gate electrode and a second gate electrode are connected by a gate connecting wiring and the source connecting wiring and the drain connecting wiring are provided at positions except a region overlapped with the first gate electrode, the second gate electrode and the gate connecting wiring.

Abstract: There is provided a CMOSFET device with a threshold voltage controlled by means of its gate stack configuration and a method of fabricating the same. The CMOSFET device comprises: a semiconductor substrate; am interface layer grown on the silicon substrate; a first high-k gate dielectric layer deposited on the interface layer; a very thin metal layer deposited on the first high-k gate dielectric layer; a second high-k gate dielectric layer deposited on the very thin metal layer; and a gate electrode layer deposited on the second high-k gate dielectric layer.

Abstract: The present invention relates to a semiconductor device structure and a method for manufacturing the same; the structure comprises: a semiconductor substrate on which a device structure is formed thereon; an interlayer dielectric layer formed on the device structure, wherein a trench is formed in the interlayer dielectric layer, the trench comprises an incorporated via trench and a conductive wiring trench, and the conductive wiring trench is positioned on the via trench; and a conductive layer filled in the trench, wherein the conductive layer is electrically connected with the device structure; wherein the conductive layer comprises a conductive material and a nanotube/wire layer surrounded by the conductive material. Wherein, the conductive layer comprises a conductive material and a nanotube/wire layer surrounded by the conductive material.