Abstract: A resistance welding apparatus includes a welding gun having a first electrode tip serving as a first welding electrode, a second electrode tip serving as a second welding electrode, and a current branching electrode. The current branching electrode has an annular shape and is disposed in surrounding relation to the first electrode tip. The first electrode tip and the current branching electrode abut against a thinnest workpiece disposed on an outermost side of a stacked assembly that is resistance-welded by the resistance welding apparatus, and have opposite polarities to each other. When an electric current is passed from the first electrode tip to the second electrode tip and through the stacked assembly, a branched electric current flows from the first electrode tip to the current branching electrode.

Abstract: Microphone arrays (MAs) are described that position and vent microphones so that performance of a noise suppression system coupled to the microphone array is enhanced. The MA includes at least two physical microphones to receive acoustic signals. The physical microphones make use of a common rear vent (actual or virtual) that samples a common pressure source. The MA includes a physical directional microphone configuration and a virtual directional microphone configuration. By making the input to the rear vents of the microphones (actual or virtual) as similar as possible, the real-world filter to be modeled becomes much simpler to model using an adaptive filter.

Abstract: An earpiece (100) is provided. The earpiece can include an Ambient Sound Microphone (111) configured to capture ambient sound, an Ear Canal Microphone (123) configured to capture internal sound in the ear canal, a memory (208) configured to record at least a portion of the history of the ambient sound and the internal sound, and a processor (121) configured to save a recent portion of the history responsive to an event.

Abstract: A semiconductor device includes: a gate pattern over a substrate; recess patterns provided in the substrate at both sides of the gate pattern, each having a side surface extending below the gate pattern; and a source and a drain filling the recess patterns, and forming a strained channel under the gate pattern.

Abstract: A solid-state imaging device including a first transfer electrode portion and a second transfer electrode portion having a pattern area ratio higher than that of the first transfer electrode portion. The first transfer electrode portion includes a plurality of first transfer electrodes having a single-layer structure of metal material. The second transfer electrode portion includes a plurality of second transfer electrodes having a single-layer structure of polycrystalline silicon or amorphous silicon.

Abstract: A method is disclosed for creating a semiconductor device structure with an oxide-filled large deep trench (OFLDT) portion having trench size TCS and trench depth TCD. A bulk semiconductor layer (BSL) is provided with a thickness BSLT>TCD. A large trench top area (LTTA) is mapped out atop BSL with its geometry equal to OFLDT. The LTTA is partitioned into interspersed, complementary interim areas ITA-A and ITA-B. Numerous interim vertical trenches of depth TCD are created into the top BSL surface by removing bulk semiconductor materials corresponding to ITA-B. The remaining bulk semiconductor materials corresponding to ITA-A are converted into oxide. If any residual space is still left between the so-converted ITA-A, the residual space is filled up with oxide deposition. Importantly, the geometry of all ITA-A and ITA-B should be configured simple and small enough to facilitate fast and efficient processes of oxide conversion and oxide filling.

Abstract: A method for manufacturing a biosensor includes forming a silicon nanowire channel, etching a first conductivity-type single crystalline silicon layer which is a top layer of a Silicon-On-Insulator (SOI) substrate to form a first conductivity-type single crystalline silicon line pattern, doping both sidewalls of the first conductivity-type single crystalline silicon line pattern with impurities of a second conductivity-type opposite to the first conductivity-type to form a second conductivity-type channel, forming second conductivity-type pads for forming electrodes at both ends of the first conductivity-type single crystalline silicon line pattern, forming, in an undoped region of the first conductivity-type single crystalline silicon line pattern, a first electrode for applying a reverse-bias voltage to insulate the first conductivity-type single crystalline silicon line pattern and the second conductivity-type channel from each other, and forming second electrodes for applying a bias voltage across the sec

Abstract: A CMOS image sensor, in which an implantation process is performed on substrate under isolation structures each disposed between two adjacent photosensor cell structures. The implantation process is a destructive implantation to form lattice effects/trap centers. No defect repair process is carried out after the implantation process is performed. The implants can reside at the isolation structures or in the substrate under the isolation structures. Dark leakage and crosstalk are thus suppressed.

Abstract: A voice signal transmitting/receiving apparatus includes: a device body; a speaker array arranged in the device body and including a plurality of arrayed speaker units; and a microphone array arranged in the device body and including a plurality of arrayed microphones. By thus integrating the speaker array and the microphone array, it is possible to improve the operability of a user, to acquaint the user relatively easily with the error in the set position and to make the device compact.

Abstract: Photodetector arrays, image sensors, and other apparatus are disclosed. In one aspect, an apparatus may include a surface to receive light, a plurality of photosensitive regions disposed within a substrate, and a material coupled between the surface and the plurality of photosensitive regions. The material may receive the light. At least some of the light may free electrons in the material. The apparatus may also include a plurality of discrete electron repulsive elements. The discrete electron repulsive elements may be coupled between the surface and the material. Each of the discrete electron repulsive elements may correspond to a different photosensitive region. Each of the discrete electron repulsive elements may repel electrons in the material toward a corresponding photosensitive region. Other apparatus are also disclosed, as are methods of use, methods of fabrication, and systems incorporating such apparatus.

Abstract: A microphone in a miniaturized form is described herein. The microphone includes a flat carrier substrate having a first recess extending through the carrier substrate. The microphone includes a first electro-acoustic transducer on a first surface of the carrier substrate and at least partially overlapping the first recess. The microphone also includes a cap on a second surface opposite the first surface having a tight seal with the second surface and spanning the first recess. The cap includes at least one metallic layer for electromagnetic shielding.

Abstract: A fan-out unit which can control a resistance difference among channels with efficient space utilization and a thin-film transistor (TFT) array substrate having the fan-out unit are presented. The fan-out unit includes: an insulating substrate; a first wiring layer which is formed on the insulating substrate and connected to a pad; a second wiring layer which is formed on the insulating substrate and connected to a TFT; and a resistance controller which is connected between the first wiring layer and the second wiring layer and includes a plurality of first resistors extending parallel to the first wiring layer and a plurality of second resistors extending perpendicular to the first resistors and alternately connecting to the first resistors, wherein the first resistors are longer than the second resistors.

Abstract: An active solid heatsink device and fabricating method thereof is related to a high-effective solid cooling device, where heat generated by a heat source with a small area and a high heat-generating density diffuses to a whole substrate using a heat conduction characteristic of hot electrons of a thermionic (TI) structure, and the thermionic (TI) structure and a thermo-electric (TE) structure share the substrate where the heat diffuses to. Further, the shared substrate serves as a cold end of the TE structure, and the heat diffusing to the shared substrate is pumped to another substrate of the TE structure serving as a hot end of the TE structure.

Abstract: Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.

Abstract: A sound transducer for the transmission of audio frequency signals with a pressure-voltage transducer is provided. This pressure-voltage transducer is disposed on a supporting plate and at least partially embedded in a sound-insulating, substantially incompressible material, for example a gel. The supporting plate rests herein in contact on a body part, for example a jaw or skull bone, of a person. If this person conducts a conversation, the vibrations of the bone generated through the conversation are transmitted to a supporting plate. This supporting plate subsequently transmits the vibrations onto the pressure-voltage transducer, for example a piezoelectric element or an electret element.

Abstract: A semiconductor chip package comprises a lead frame having a chip carrier having a first surface and an opposite second surface. A first semiconductor chip is mounted on the first surface, having a plurality of bonding pads thereon, wherein the first semiconductor chip has an area larger that that of the chip carrier. A package substrate has a central region attached to the second surface of the chip carrier, having an area larger than that of the first semiconductor chip, wherein the package substrate comprises a plurality of fingers on a top surface thereof in a marginal region of the package substrate, which are arranged in an array with a row of inner fingers adjacent to the first semiconductor chip and a row of outer fingers adjacent to an edge of the package substrate, wherein the inner and outer fingers are electrically connected to the bonding pads of the first semiconductor chip and the lead frame respectively.

Abstract: A programmable crosspoint device with an integral diode includes a first crossbar, a second crossbar, a metallic interlayer, and a switching oxide layer interposed between the first crossbar and the metallic interlayer. The switching oxide layer has a low resistance state and high resistance state. The programmable crosspoint device also includes an integral diode which is interposed between the second crossbar layer and the metallic interlayer, the integral diode being configured to limit the flow of leakage current through the programmable crosspoint device in one direction. A method for forming a programmable crosspoint device with an integrated diode is also provided.

Abstract: Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0?y?1); a carrier supply layer 13 composed of AlxGa1-xN (0?x?1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x<NA×?×t [cm?2]<5.6×1013x, where x denotes an Al compositional ratio of the carrier supply layer, t denotes a thickness of the p-type layer, NA denotes an impurity concentration, and ? denotes an activation ratio.

Abstract: A method is provided for simultaneously fabricating a flash storage element, an NFET and a PFET having metal gates with different workfunctions. A first gate metal layer of the NFET having a first workfunction can be deposited simultaneously with a first metal layer for forming the floating gate of the flash storage element. A second gate metal layer of the PFET having a second workfunction different from the first workfunction can be deposited simultaneously with a second metal layer for forming the control gate of the flash storage element. A semiconductor layer can then be deposited over the first and second metal layers and gate metal layers and patterned to form first, second and third gates. Source and drain regions of the flash storage element, the NFET and the PFET can then be formed adjacent to the first, second and third gates, respectively.

Abstract: A resistance switching memory is introduced herein. The resistance switching memory includes a highly-insulating or resistance-switching material formed to cover the sidewall of a patterned metal line, and extended alongside a dielectric layer sidewall to further contact a portion of the top surface of the lower electrode. The other part of the top surface of the lower electrode is covered by an insulating layer between the top electrode and the lower electrode. An oxygen gettering metal layer in the lower electrode occupies a substantial central part of the top surface of the lower electrode and is partially covered by the highly-insulating or resistance-switching material. A switching area is naturally very well confined to the substantial central part of the oxygen gettering metal layer of the lower electrode.