Patents Examined by Luan C Thai
  • Patent number: 10892215
    Abstract: An apparatus including a circuit structure including a device stratum; and a contact coupled to a supply line and routed through the device stratum and coupled to at least one device on a first side. A method including providing a supply from a package substrate to at least one transistor in a device stratum of a circuit structure; and distributing the supply to the at least one transistor using a supply line on an underside of the device stratum and contacting the at least one transistor on a device side by routing a contact from the supply line through the device stratum. A system including a package substrate, and a die including at least one supply line disposed on an underside of a device stratum and routed through the device stratum and coupled to at least one of a plurality of transistor devices on the device side.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventors: Donald W. Nelson, Mark T. Bohr, Patrick Morrow
  • Patent number: 10886373
    Abstract: The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. A semiconductor layer of a transistor is formed using a composite oxide semiconductor in which a first region and a second region are mixed. The first region includes a plurality of first clusters containing one or more of indium, zinc, and oxygen as a main component. The second region includes a plurality of second clusters containing one or more of indium, an element M (M represents Al, Ga, Y, or Sn), zinc, and oxygen. The first region includes a portion in which the plurality of first clusters are connected to each other. The second region includes a portion in which the plurality of second clusters are connected to each other.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: January 5, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasutaka Nakazawa, Masashi Oota
  • Patent number: 10879158
    Abstract: Certain aspects of the present disclosure generally relate to a chip package having a split conductive pad for coupling to a device terminal. An example chip package generally includes a layer, a first plurality of conductive pads disposed on the layer, at least one conductive trace disposed on the layer and between the first plurality of conductive pads, and an electrical component having a first terminal coupled to the first plurality of conductive pads and disposed above the at least one conductive trace.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: December 29, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Aniket Patil, Hong Bok We, Kuiwon Kang, Zhijie Wang
  • Patent number: 10872870
    Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: December 22, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yi-Cheih Chen, Sung-Huan Sun, Cheng-An Chang, Chien-Hung Wu, Fu-Tang Huang
  • Patent number: 10871691
    Abstract: A display device includes a substrate including pixel electrodes, a first data line extending in the first direction and through which a data signal is supplied to the pixel electrodes in a first region that is close to one ends of the pixel electrodes in the first direction, and a second data line extending in the first direction and through which a data signal is supplied to the pixel electrodes in a second region that is closer to another ends of the pixel electrodes in the first direction than the first region is, and a driver circuit disposed close to the one ends of the pixel electrodes and configured to supply a data signal to each of the pixel electrodes through the first data line and the second data line. The first data line and the second data line are overlapped with each other in the first region.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: December 22, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Masakatsu Tominaga
  • Patent number: 10867944
    Abstract: The present disclosure provides a semiconductor structure, including a substrate, a conductive pad, a passivation layer, a recess, a bump pad, and a conductive bump. The conductive pad is disposed over the substrate. The passivation layer is disposed over the substrate and partially covers the conductive pad. The recess extends through the passivation layer and extends at least partially into the conductive pad. The bump pad is disposed over the passivation layer and within the recess; and the conductive bump is disposed over the bump pad. A method of manufacturing the semiconductor structure is also provided.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Tung-Jiun Wu
  • Patent number: 10861759
    Abstract: A circuit module includes: a substrate including a wiring pattern; a first region in which a first electronic component is mounted on one major surface of the substrate; a second region in which a second electronic component, which is taller than the first electronic component, is mainly mounted on the one major surface of the substrate; a first conductor provided in the first region and electrically connected with the wiring pattern; and sealing resin that seals the first electronic component, the second electronic component, and the first conductor. Sealing resin sealing the first region is formed to be shorter than sealing resin sealing the second region, part of the first conductor is exposed on a surface of the sealing resin, wiring is formed on the surface of the sealing resin, and the first conductor the part of which is exposed is electrically connected with the wiring.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: December 8, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kaneo Nomiyama, Kazushige Sato, Yuya Eshita, Nobumitsu Amachi
  • Patent number: 10854566
    Abstract: A pre-conductive array disposed on a target circuit substrate comprises a plurality of conductive electrode groups disposed on the target circuit substrate, and at least a conductive particle dispose on each of conductive electrodes of a part or all of the conductive electrode groups. The at least a conductive particle and the corresponding conductive electrode form a pre-conductive structure, and the pre-conductive structures form the pre-conductive array.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: December 1, 2020
    Assignee: Ultra Display Technology Corp.
    Inventor: Hsien-Te Chen
  • Patent number: 10847444
    Abstract: A through electrode substrate includes a substrate having a through hole extending through between a first face and a second face, a diameter of the through hole not having a minimum value inside the through hole; and a conductor arranged inside the through hole, wherein the through hole has a shape having a value obtained by summing a first to an eighth inclination angle at a first to an eighth position, respectively, of an inner face of the through hole of 8.0° or more, each of the first to the eighth inclination angle is an angle of the inner face with respect to a center axis of the through hole, and the first to the eighth position correspond to positions at distances of 6.25%, 18.75%, 31.25%, 43.75%, 56.25%, 68.75%, 81.25%, and 93.75%, respectively, from the first face in a section from the first face to the second face.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: November 24, 2020
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventor: Satoru Kuramochi
  • Patent number: 10847457
    Abstract: A structure and method for the formation and use of fuses within a semiconductor device is provided. The fuses may be formed within the third metal layer and are formed so as to be arranged perpendicularly to active devices located on an underlying semiconductor substrate. Additionally, the fuses within the third metal layer may be formed thicker than an underlying second metal layer.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon Jhy Liaw
  • Patent number: 10840133
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate; a first conductive feature and a second conductive feature disposed on the semiconductor substrate; and a staggered dielectric feature interposed between the first and second conductive feature. The staggered dielectric feature includes first dielectric layers and second dielectric layers being interdigitated. The first dielectric layers include a first dielectric material and the second dielectric layers include a second dielectric material being different from the first dielectric material.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Chang Lin, Teng-Chun Tsai, Wei-Hao Wu
  • Patent number: 10833042
    Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first and a second semiconductor structures. The first semiconductor structure includes a first interconnect layer including first interconnects. The first semiconductor structure further includes a first bonding layer including first bonding contacts. Each first interconnect is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnects. The second semiconductor structure further includes a second bonding layer including second bonding contacts. At least one second bonding contact is in contact with a respective second interconnect. At least another second bonding contact is separated from the second interconnects. The semiconductor device further includes a bonding interface between the first and second bonding layers.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: November 10, 2020
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Tao Wang, Si Ping Hu, Jia Wen Wang, Shi Qi Huang, Jifeng Zhu, Jun Chen, Zi Qun Hua
  • Patent number: 10825758
    Abstract: A semiconductor device includes two or more semiconductor elements, a lead with island portions on which the semiconductor elements are mounted, a heat dissipation member for dissipating heat from the island portions, a bonding layer bonding the island portions and the heat dissipation member, and a sealing resin covering the semiconductor elements, the island portions and a part of the heat dissipation member. The bonding layer includes mutually spaced individual regions provided for the island portions, respectively.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: November 3, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Shoji Yasunaga, Akihiro Koga
  • Patent number: 10825904
    Abstract: Provided is a semiconductor device including a buffer region. Provided is a semiconductor device including: semiconductor substrate of a first conductivity type; a drift layer of the first conductivity type provided in the semiconductor substrate; and a buffer region of the first conductivity type provided in the drift layer, the buffer region having a plurality of peaks of a doping concentration, wherein the buffer region has: a first peak which has a predetermined doping concentration, and is provided the closest to a back surface of the semiconductor substrate among the plurality of peaks; and a high-concentration peak which has a higher doping concentration than the first peak, and is provided closer to an upper surface of the semiconductor substrate than the first peak is.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 3, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yasunori Agata, Takashi Yoshimura, Hiroshi Takishita
  • Patent number: 10818631
    Abstract: A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a first substrate; a first adhesive layer disposed on the surface of the first substrate; a first buffer layer disposed on the surface of the first adhesive layer; and a first bonding layer disposed on the surface of the first buffer layer, wherein the densities of the first adhesive layer and the first buffer layer are greater than that of the first bonding layer. The first adhesive layer of the semiconductor structure has higher adhesion with the first substrate and the first buffer layer, and the first buffer layer and the first bonding layer exhibit higher adhesion, which are beneficial to improve the performance of the semiconductor structure.
    Type: Grant
    Filed: April 7, 2019
    Date of Patent: October 27, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xinsheng Wang, Li Zhang, Gaosheng Zhang, Xianjin Wan, Ziqun Hua, Jiawen Wang, Taotao Ding, Hongbin Zhu, Weihua Cheng, Shining Yang
  • Patent number: 10818634
    Abstract: The present disclosure provides a display panel, a method for manufacturing the display panel, and a display device. The display panel includes a substrate; a printed circuit board; a chip on film; an anisotropic conductive adhesive layer, connected between the chip on film and the substrate, and between the chip on film and the printed circuit board.
    Type: Grant
    Filed: January 13, 2019
    Date of Patent: October 27, 2020
    Assignees: HKC Corporation Limited, Chongqing HKC Optoelectronics Technology Co., Ltd.
    Inventor: Shishuai Huang
  • Patent number: 10811379
    Abstract: A semiconductor package includes a semiconductor chip including a body, a connection pad, a passivation film, a first connection bump disposed, and a first coating layer; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure including an insulating layer, a redistribution layer, and a connection via. The first connection bump includes a low melting point metal, the redistribution layer and the connection via include a conductive material, and the low melting point metal has a melting point lower than a melting point of the conductive material.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: October 20, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo Il Kim, Yong Ho Baek, Won Wook So, Young Sik Hur
  • Patent number: 10811380
    Abstract: The present invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a first substrate; a first adhesive layer disposed on a surface of the first substrate; and a first bonding layer disposed on a surface of the first adhesive layer. A density of the first adhesive layer is greater than a density of the first bonding layer. The first adhesive layer of the semiconductor structure has higher adhesion with the first substrate and first bonding layer, such that it is advantageous to improve a performance of the semiconductor structure.
    Type: Grant
    Filed: April 7, 2019
    Date of Patent: October 20, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xinsheng Wang, Li Zhang, Gaosheng Zhang, Xianjin Wan, Ziqun Hua, Jiawen Wang, Taotao Ding, Hongbin Zhu, Weihua Cheng, Shining Yang
  • Patent number: 10811313
    Abstract: A method of forming conductive traces comprises forming a seed material over a surface of a substrate, forming a patterned mask material over the seed material to define trenches leaving portions of the seed material within the trenches exposed, and depositing a conductive material over the exposed seed material in the trenches to form conductive traces. At least a portion of the patterned mask material is removed, a barrier formed over side surfaces and upper surfaces of the conductive traces, and exposed portions of the seed material are removed. Conductive traces and structures incorporating conductive traces are also disclosed.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: October 20, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Christopher J. Gambee
  • Patent number: 10811342
    Abstract: A semiconductor package includes a semiconductor die having a semiconductor device, and first and second contact pads arranged on opposite surfaces of the die. The semiconductor die is embedded in a dielectric layer. The semiconductor package also includes one or more first package contact pads and one or more second package contact pads arranged on a first major surface of the semiconductor package. The first contact pad of the die is coupled to the one or more first package contact pads, and the second contact pad of the die is coupled to the one or more second package contact pads. In operation, the semiconductor device causes a current path between the first contact pad and the second contact pad. The package contact pads are arranged on the first major surface of the semiconductor package to provide multiple non-parallel current paths.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: October 20, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Sergey Yuferev, Robert Fehler, Petteri Palm