Patents Examined by Luan C Thai
  • Patent number: 10354891
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming a filling material, such as an underfill, between a carrier and a plurality of electronic components and filling the filling material in a space between the electronic components to form a spacing portion. The spacing portion has a first segment and a second segment separated from each other to serve as a stress buffer zone. Therefore, when an encapsulation layer encapsulating the electronic components is subsequently ground, the present disclosure can effectively prevent the electronic components from being cracked due to stresses induced by the external grinding force.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: July 16, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Po-Hao Wang, Chih-Jen Yang, Yu-Chih Cheng, Chee-Key Chung, Chang-Fu Lin
  • Patent number: 10355142
    Abstract: First and second p-type anode layers (2,3) are provided side by side on a drift layer (1). N-type cathode layer (5) and p-type cathode layer (6) are provided side by side below the drift layer (1). An n-type buffer layer (7) is provided between the drift layer (1) and the n-type cathode layer (5) and between the drift layer (1) and the p-type cathode layer (6). The first p-type anode layer (2,2a,2b) has a greater diffusion depth than a diffusion depth of the second p-type anode layer (3). The first p-type anode layer (2,2a,2b) has a greater impurity concentration than an impurity concentration of the second p-type anode layer (3). The n-type cathode layer (5) has a greater diffusion depth than a diffusion depth of the p-type cathode layer (6). The n-type cathode layer (5) has a greater impurity concentration than an impurity concentration of the p-type cathode layer (6).
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: July 16, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventor: Fumihito Masuoka
  • Patent number: 10354965
    Abstract: The present disclosure describes an bonding pad formation method that incorporates an tantalum (Ta) conductive layer to block mobile ionic charges generated during the aluminum-copper (AlCu) metal fill deposition. For example, the method includes forming one or more interconnect layers over a substrate and forming a dielectric over a top interconnect layer of the one or more interconnect layers. A first recess is formed in the dielectric to expose a line or a via from the top interconnect layer. A conductive layer is formed in the first recess to form a second recess that is smaller than the first recess. A barrier metal layer is formed in the second recess to form a third recess that is smaller than the second recess. A metal is formed to fill the third recess.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih Wei Bih, Chun-Chih Lin, Sheng-Wei Yeh, Yen-Yu Chen, Chih-Wei Lin, Wen-Hao Cheng
  • Patent number: 10347528
    Abstract: Methods of forming an interconnect of an IC are disclosed. The methods etch a wire trench opening partially into an ILD layer using a hard mask, and form a metal liner sidewall spacer on sidewalls of the wire trench opening, prior to etching via openings that create a via-wire opening with the wire trench opening. The metal liner sidewall spacer protects against chamfering during the via etch and/or removal of an etch stop layer over conductive structures in an underlying ILD layer. In one embodiment, a barrier liner is deposited over the metal liner sidewall spacer, creating a double layered sidewall spacer on the sidewalls of the wire trench opening portion of the via-wire opening. A conductor is deposited to form a unitary via-wire conductive structure. An interconnect includes the double layered sidewall spacer on the sidewalls of a wire trench opening portion of the via-wire conductive structure.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sunil K. Singh, Ravi P. Srivastava, Sipeng Gu, Akshey Sehgal
  • Patent number: 10347585
    Abstract: A fan-out semiconductor package includes: a first semiconductor chip having a first active surface having first connection pads; a first encapsulant encapsulating the first semiconductor chip; a first connection member disposed on the first active surface and including a first redistribution layer electrically connected to the first connection pads; a second semiconductor chip having a second active surface having second connection pads; a second encapsulant covering the first connection member and encapsulating the second semiconductor chip; a second connection member disposed on the second active surface and including a second redistribution layer electrically connected to the second connection pads; and a third via penetrating through the second encapsulant, connecting the first redistribution layer and the second redistribution layer to each other, and including a metal post connected to the first redistribution layer and a via conductor disposed on the metal post and connected to the second redistributio
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: July 9, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seung Wan Shin, Seung Chul Oh
  • Patent number: 10340198
    Abstract: The invention provides a semiconductor package and a method for fabricating the same. The semiconductor package includes a redistribution layer (RDL) structure, a semiconductor die, a molding compound and a supporter. The RDL structure has a first surface and a second surface opposite to the first surface. The semiconductor die is disposed on the first surface of the RDL structure and electrically coupled to the RDL structure. The molding compound is positioned overlying the semiconductor die and the first surface of the RDL structure. The supporter is positioned beside the semiconductor die and in contact with the first surface of the RDL structure.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: July 2, 2019
    Assignee: MEDIATEK INC.
    Inventors: Ta-Jen Yu, Wen-Sung Hsu
  • Patent number: 10332783
    Abstract: A method of manufacturing a semiconductor device is provided. The method comprises arranging an insulator, forming a hole in the insulator, first exposing for exposing a first portion of a photoresist arranged on the insulator, second exposing for exposing a second portion of the photoresist, after the first and second exposing, forming a trench in the insulator in accordance with etching the insulator using a resist pattern formed by developing the photoresist as a mask and embedding a conductor in the hole and the trench. The trench includes a first trench corresponding to the exposure of the first portion of the resist pattern and a second trench corresponding to the exposure of the second portion of the resist pattern. The first and second trench each communicate with the hole and the hole is deeper than the first and second trench.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: June 25, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Nobuaki Kakinuma
  • Patent number: 10332792
    Abstract: A method of forming conductive traces comprises forming a seed material over a surface of a substrate, forming a patterned mask material over the seed material to define trenches leaving portions of the seed material within the trenches exposed, and depositing a conductive material over the exposed seed material in the trenches to form conductive traces. At least a portion of the patterned mask material is removed, a barrier formed over side surfaces and upper surfaces of the conductive traces, and exposed portions of the seed material are removed. Conductive traces and structures incorporating conductive traces are also disclosed.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Christopher J. Gambee
  • Patent number: 10325847
    Abstract: Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: June 18, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Eric H. Freeman, Michael A. Smith
  • Patent number: 10325840
    Abstract: An apparatus including a circuit structure including a device stratum; and a contact coupled to a supply line and routed through the device stratum and coupled to at least one device on a first side. A method including providing a supply from a package substrate to at least one transistor in a device stratum of a circuit structure; and distributing the supply to the at least one transistor using a supply line on an underside of the device stratum and contacting the at least one transistor on a device side by routing a contact from the supply line through the device stratum. A system including a package substrate, and a die including at least one supply line disposed on an underside of a device stratum and routed through the device stratum and coupled to at least one of a plurality of transistor devices on the device side.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Donald W. Nelson, Mark T. Bohr, Patrick Morrow
  • Patent number: 10325872
    Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: June 18, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yi-Cheih Chen, Sung-Huan Sun, Cheng-An Chang, Chien-Hung Wu, Fu-Tang Huang
  • Patent number: 10325841
    Abstract: According to an embodiment of the present invention, there is provided a semiconductor device having a first semiconductor component and a second semiconductor component which are mounted on a wiring substrate. The first semiconductor component has a first terminal for transmitting a first signal between the first semiconductor component and the outside and a second terminal for transmitting a second signal between the first semiconductor component and the second semiconductor component. In addition, the second semiconductor component has a third terminal for transmitting the second signal between the second semiconductor component and the first semiconductor component. Further, the first signal is transmitted at a higher frequency than the second signal. Furthermore, the second terminal of the first semiconductor component and the third terminal of the second semiconductor component are electrically connected to each other via the first wiring member.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: June 18, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuyuki Nakagawa, Katsushi Terajima, Keita Tsuchiya, Yoshiaki Sato, Hiroyuki Uchida, Yuji Kayashima, Shuuichi Kariyazaki, Shinji Baba
  • Patent number: 10312196
    Abstract: A semiconductor package may include a package substrate to which a first semiconductor chip is attached, an encapsulant covering the first semiconductor chip, and an indicator disposed within the semiconductor package. A side surface of the indicator is exposed at a side surface of the semiconductor package, and a width of a vertical section of the indicator parallel with the exposed side surface of the indicator varies as the vertical section of the indicator becomes farther from the side surface of the semiconductor package.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: June 4, 2019
    Assignee: SK hynix Inc.
    Inventors: Sukwon Lee, Bok Gyu Min
  • Patent number: 10312221
    Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device includes a stack of plural semiconductor chips. Each two adjacent semiconductor chips of the plural semiconductor chips is electrically connected by plural interconnects and physically connected by a first insulating bonding layer. A first stack of dummy chips is positioned opposite a first side of the stack of semiconductor chips and separated from the plural semiconductor chips by a first gap. Each two adjacent of the first dummy chips are physically connected by a second insulating bonding layer. A second stack of dummy chips is positioned opposite a second side of the stack of semiconductor chips and separated from the plural semiconductor chips by a second gap. Each two adjacent of the second dummy chips are physically connected by a third insulating bonding layer.
    Type: Grant
    Filed: December 17, 2017
    Date of Patent: June 4, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Rahul Agarwal, Kaushik Mysore Srinivasa Setty, Milind S. Bhagavat, Brett P. Wilkerson
  • Patent number: 10304744
    Abstract: Various methods and structures for fabricating a plurality of vertical fins in a vertical fin pattern on a semiconductor substrate where the vertical fins in the vertical fin pattern are separated by wide-open spaces, along a critical dimension, in a low duty cycle of 1:5 or lower. Adjacent vertical fins in the vertical fin pattern can be all separated by respective wide-open spaces, along a critical dimension, in a low duty cycle, and wherein pairs of adjacent vertical fins in the vertical fin pattern, along the critical dimension, are separated by a constant pitch value at near zero tolerance.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Praveen Joseph, Ekmini Anuja De Silva, Fee Li Lie, Stuart A. Sieg, Yann Mignot, Indira Seshadri
  • Patent number: 10304766
    Abstract: A semiconductor package includes a circuit pattern extending in a horizontal direction. The circuit pattern is conductive. A first insulation layer is disposed on the circuit pattern. A semiconductor chip is disposed on the first installation layer. The first insulation layer includes first protrusions which protrude from a bottom surface of the first insulation layer, penetrate through at least a portion of the circuit pattern, and have a mesh structure. A second protrusion protrudes from the bottom surface of the first insulation layer and penetrates at least a portion of the circuit pattern. The second protrusion is spaced apart from the semiconductor chip in the horizontal direction. The second protrusion has a width in the horizontal direction wider than that of each of the first protrusions.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bu-won Kim, Dae-ho Lee, Hee-jin Lee
  • Patent number: 10304769
    Abstract: Embodiments herein may relate to a package that includes a package substrate with a first die on a first side of the package substrate and a second die on a second side of the package substrate. Solder balls may be coupled with the second side of the package substrate and the second die such that the solder balls are approximately coplanar. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: May 28, 2019
    Assignee: INTEL CORPORATION
    Inventors: Robert L. Sankman, Allan A. Ovrom, III, Robert Starkston, Oren Arad
  • Patent number: 10297554
    Abstract: A semiconductor package including a marking film and a method of fabricating the same are provided wherein a marking film including a thermoreactive layer may be applied to a molding layer to protect a semiconductor chip under the molding layer and to efficiently perform a marking process. The thickness of the molding layer may thereby be reduced so the entire thickness of the semiconductor package may be reduced. Also, it is possible to prevent warpage of the semiconductor package through the marking film, provide the surface of the semiconductor package with gloss and freely adjust the color of the surface of the semiconductor package.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: May 21, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yeongseok Kim
  • Patent number: 10297544
    Abstract: Provided is an integrated fan-out package including a die, an insulating encapsulation, a redistribution circuit structure, a conductive terminal, and a barrier layer. The die is encapsulated by the insulating encapsulation. The redistribution circuit structure includes a redistribution conductive layer. The redistribution conductive layer is disposed in the insulating encapsulation and extending from a first surface of the insulating encapsulation to a second surface of the insulating encapsulation. The conductive terminal is disposed over the second surface of the insulating encapsulation. The barrier layer is sandwiched between the redistribution conductive layer and the conductive terminal. A material of the barrier layer is different from a material of the redistribution conductive layer and a material of the conductive terminal. A method of fabricating the integrated fan-out package is also provided.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Wen Wu, Hung-Jui Kuo, Ming-Che Ho
  • Patent number: 10290611
    Abstract: In an embodiment, a package includes a first package structure including a first die having a first active side and a first back-side, the first active side including a first bond pad and a first insulating layer a second die bonded to the first die, the second die having a second active side and a second back-side, the second active side including a second bond pad and a second insulating layer, the second active side of the second die facing the first active side of the first die, the second insulating layer being bonded to the first insulating layer through dielectric-to-dielectric bonds, and a conductive bonding material bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature lower than reflow temperatures of the first and second bond pads.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chih-Hang Tung, Kuo-Chung Yee