Patents Examined by Luan C Thai
  • Patent number: 11211351
    Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: December 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shih-Fan Kuan, Yi-Jen Lo
  • Patent number: 11211371
    Abstract: In an embodiment, a structure includes: a graphics processor device; a passive device coupled to the graphics processor device, the passive device being directly face-to-face bonded to the graphics processor device; a shared memory device coupled to the graphics processor device, the shared memory device being directly face-to-face bonded to the graphics processor device; a central processor device coupled to the shared memory device, the central processor device being directly back-to-back bonded to the shared memory device, the central processor device and the graphics processor device each having active devices of a smaller technology node than the shared memory device; and a redistribution structure coupled to the central processor device, the shared memory device, the passive device, and the graphics processor device.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Wei Ling Chang, Chuei-Tang Wang, Chieh-Yen Chen
  • Patent number: 11205619
    Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first and a second semiconductor structures. The first semiconductor structure includes a first interconnect layer including first interconnects. At least one first interconnect is a first dummy interconnect. The first semiconductor structure further includes a first bonding layer including first bonding contacts. Each first interconnect is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnects. At least one second interconnect is a second dummy interconnect. The second semiconductor structure further includes a second bonding layer including second bonding contacts. Each second interconnect is in contact with a respective second bonding contact. The semiconductor device further includes a bonding interface between the first and second bonding layers.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: December 21, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Tao Wang, Si Ping Hu, Jia Wen Wang, Shi Qi Huang, Jifeng Zhu, Jun Chen, Zi Qun Hua
  • Patent number: 11189585
    Abstract: An Integrated Circuit (IC) device comprising a first component, the first component comprising a first dielectric and a plurality of adjacent first interconnect structures within the first dielectric. The IC device comprising a second component, the second component comprising a second dielectric and a plurality of adjacent second interconnect structures within the second dielectric. A first of the second interconnect structures is in direct contact with a first of the first interconnect structures at a bond interface between the first and second components. A second of the first interconnect structures is set back a distance from a plane of the bond interface.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: November 30, 2021
    Assignee: Intel Corporation
    Inventors: Brennen K. Mueller, Adel Elsherbini, Mauro Kobrinsky, Johanna Swan, Shawna Liff, Pooya Tadayon
  • Patent number: 11183570
    Abstract: The present disclosure relates to a semiconductor structure includes a substrate with a top surface and first and second devices formed on the top surface of the substrate. The semiconductor structure also includes a deep isolation structure formed in the substrate and between the first and second devices. The deep isolation structure includes a top portion formed at the top surface and having a top width and a bottom surface having a bottom width larger than the top width.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh Singh, Tsung-Han Tsai, Kun-Tsang Chuang
  • Patent number: 11171107
    Abstract: A semiconductor package includes: a semiconductor chip including a body having a first surface and a second surface, opposing the first surface, a connection pad disposed on the first surface of the body, and an extension pad disposed on the connection pad; and a connection structure including an insulating layer disposed on the first surface of the body of the semiconductor chip, a redistribution via penetrating through the insulating layer and having one side thereof in contact with the extension pad, and a redistribution layer disposed on the insulating layer and having a via pad in contact with the other side of the redistribution via, wherein a horizontal cross-sectional area of extension pad of the semiconductor chip is greater than a horizontal cross-sectional area of the connection pad of the semiconductor chip.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: November 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gyu Jin Choi, Sung Hoan Kim, Chang Eun Joo, Chil Woo Kwon, Young Kyu Lim, Sung Uk Lee
  • Patent number: 11164824
    Abstract: A package structure includes a circuit substrate and a semiconductor package. The semiconductor package is disposed on the circuit substrate, and includes a plurality of semiconductor dies, an insulating encapsulant and a connection structure. The insulating encapsulant comprises a first portion and a second portion protruding from the first portion, the first portion is encapsulating the plurality of semiconductor dies and has a planar first surface, and the second portion has a planar second surface located at a different level than the planar first surface. The connection structure is located over the first portion of the insulating encapsulant on the planar first surface, and located on the plurality of semiconductor dies, wherein the connection structure is electrically connected to the plurality of semiconductor dies and the circuit substrate.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Kung-Chen Yeh, Li-Chung Kuo, Szu-Wei Lu, Ying-Ching Shih
  • Patent number: 11164853
    Abstract: A chip package includes a first chip, a second chip, a first molding compound, and a first distribution line. The second chip vertically or laterally overlaps the first chip. The second chip has a conductive pad. The first molding compound covers the first and second chips, and surrounds the second chip. The first molding compound has a first through hole. The conductive pad is in the first through hole. The first distribution line is located on a surface of the first molding compound facing away from the second chip, and electrically connects the conductive pad in the first through hole.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: November 2, 2021
    Assignee: XINTEC INC.
    Inventors: Chia-Ming Cheng, Shu-Ming Chang
  • Patent number: 11164821
    Abstract: A semiconductor package including a semiconductor chip having a chip pad thereon; a first insulating layer; a redistribution line pattern on the first insulating layer; a redistribution via pattern through the first insulating layer to connect the chip pad to the redistribution line pattern; a second insulating layer covering the redistribution line pattern and including a first part having a first thickness and a second part having a second thickness. the second part being inward relative to the first part; a first conductive pillar through the first part and connected to the redistribution line pattern; a second conductive pillar through the second part and connected to the redistribution line pattern; a first connection pad on the first conductive pillar; a second connection pad on the second conductive pillar; a first connection terminal contacting the first connection pad; and a second connection terminal contacting the second connection pad.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: November 2, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Boin Noh
  • Patent number: 11158609
    Abstract: The present invention relates to a three-dimensional integrated package device for a high-voltage silicon carbide power module, comprising a source substrate, first chip submodules, a first driving terminal, a first driving substrate, a ceramic housing, a metal substrate, a water inlet, a water outlet, second chip submodules, a second driving terminal, a second driving substrate and a drain substrate from top to bottom; and each first chip submodule is composed of a driving connection substrate, a power source metal block, a first driving gate metal post, second driving gate metal posts, a silicon carbide bare chip, an insulation structure and the like. A three-dimensional integrated half-bridge structure is adopted to greatly reduce corresponding parasitic parameters.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: October 26, 2021
    Assignee: XI'AN JIAOTONG UNIVERSITY
    Inventors: Laili Wang, Xiaodong Hou, Cheng Zhao, Jianpeng Wang, Dingkun Ma, Chengzi Yang, Xu Yang
  • Patent number: 11158583
    Abstract: A substrate with built-in component includes: a first wiring layer having at least one reference pattern; a first insulating layer formed on the first wiring layer; and an electronic component mounted, in a cavity formed in the first insulating layer, on the first wiring layer, wherein the at least one reference pattern includes at least one first portion crossing a side surface of the electronic component in plan view, and at least one second portion crossing a side surface of the cavity in plan view.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: October 26, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Nobutaka Aoki
  • Patent number: 11158598
    Abstract: A method to construct a 3D system, the method including: providing a base wafer; transferring a first memory wafer on top of the base wafer; thinning the first memory wafer, thus forming a thin first memory wafer; transferring a second memory wafer on top of the thin first memory wafer; thinning the second memory wafer, thus forming a thin second memory wafer; and transferring a memory control wafer on top of the thin second memory wafer; where the transferring a memory control wafer includes bonding of the memory control wafer to the thin second memory wafer, and where the bonding includes oxide to oxide and conductor to conductor bonding.
    Type: Grant
    Filed: July 11, 2021
    Date of Patent: October 26, 2021
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
  • Patent number: 11152319
    Abstract: A micro-connection structure is provided. The micro-connection structure includes an under bump metallurgy (UBM) pad, a bump and an insulating ring. The UBM pad is electrically connected to at least one metallic contact of a substrate. The bump is disposed on the UBM pad and electrically connected with the UBM pad. The insulating ring surrounds the bump and the UBM pad. The bump is separate from the insulating ring with a distance and the bump is isolated by a gap between the insulating ring and the bump.
    Type: Grant
    Filed: May 10, 2020
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hsiung Lu, Chen-Shien Chen, Chen-En Yen, Cheng-Jen Lin, Chin-Wei Kang, Kai-Jun Zhan
  • Patent number: 11145581
    Abstract: A leadless package with wettable flanks is formed by providing a substrate and plating a metal layer onto the substrate to form a contact on the substrate extending across a saw street. An encapsulant is deposited over the contact. The substrate is removed to expose the contact and encapsulant. The encapsulant and contact are singulated. In some embodiments, the substrate includes a ridge, and the contact is formed over the ridge.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: October 12, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. Truhitte, James P. Letterman, Jr.
  • Patent number: 11145645
    Abstract: Embodiments of three-dimensional (3D) memory devices having multiple memory stacks and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a first device chip, a second device chip, and a bonding interface. The first device chip includes a peripheral device and a first interconnect layer. The second device chip includes a substrate, two memory stacks disposed on opposite sides of the substrate, two memory strings each extending vertically through one of the two memory stacks, and a second interconnect layer. The bonding interface is formed vertically between the first interconnect layer of the first device chip and the second interconnect layer of the second device chip.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: October 12, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Li Hong Xiao, Bin Hu
  • Patent number: 11145579
    Abstract: An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: October 12, 2021
    Assignee: Navitas Semiconductor Limited
    Inventors: Daniel M. Kinzer, Jason Zhang, Thomas Ribarich
  • Patent number: 11133262
    Abstract: Semiconductor packages are provided. A semiconductor package includes a substrate including a first bonding region, a chip region, and a second bonding region. Moreover, the substrate includes first and second surfaces that are opposite to each other. The semiconductor package includes a pad group including a pad on the first surface in the chip region. The semiconductor package includes a semiconductor chip on the pad group. The semiconductor package includes a wire connecting the pad and the second bonding region. The wire includes a portion that extends along the second surface of the substrate. Related display devices are also provided.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: September 28, 2021
    Inventors: Ji Ah Min, Ye Chung Chung
  • Patent number: 11121119
    Abstract: The present disclosure provides a semiconductor package including a substrate, a display unit, a flexible substrate, a driving circuit, and a memory. The substrate has a first surface and a second surface opposite to each other, and the first surface has a display region and a bonding region. The display unit is disposed on the display region of the first surface. The flexible substrate is disposed below the second surface and has a connection portion extended to the bonding region of the first surface. The driving circuit is disposed on the flexible substrate and electrically connects with the display unit. The memory is disposed on the flexible substrate and electrically connects with the driving circuit.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: September 14, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chun-Liang Chen, Hann-Jye Hsu
  • Patent number: 11121064
    Abstract: A semiconductor package having a redistribution structure including a first face and a second face and a first semiconductor chip mounted on the first face. The semiconductor package may further include a first redistribution pad exposed from the second face of the redistribution structure and a second redistribution pad exposed from the second face of the redistribution structure. The semiconductor package may further include a first solder ball being in contact with the first redistribution pad and a second solder ball being in contact with the second redistribution pad. In some embodiments, a first distance of the first redistribution pad is smaller than a second distance of the second redistribution pad, the first and second distances are measured with respect to a reference plane that intersects a lower portion of the first solder ball and a lower portion of the second solder ball.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: September 14, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Ho Park, Da Hye Kim, Jin-Woo Park, Jae Gwon Jang
  • Patent number: 11114384
    Abstract: A power semiconductor die has a semiconductor body, an insulation layer on the semiconductor body, a passivation structure arranged above the insulation layer so as to expose a first insulation layer subsection that extends to an edge of the power semiconductor die, and an interruption structure in the first insulation layer subsection.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: September 7, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Blank, Christof Altstaetter, Ingmar Neumann, Rudolf Rothmaler