Abstract: A substrate including a plurality of integrated circuitry die is fabricated or otherwise provided. The individual die have bond pads. A passivation layer comprising a silicone material is formed over the bond pads. Openings are formed through the silicone material to the bond pads. After the openings are formed, the die are singulated from the substrate. In one implementation, a method of fabricating integrated circuitry includes providing a substrate comprising a plurality of integrated circuitry die. Individual of the die have bond pads. A first blanket passivation layer is formed over the substrate in contact with the bond pads. A different second blanket passivation layer comprising silicone material is formed over the first passivation layer. Openings are formed through the first and second passivation layers to the bond pads. After the openings are formed, the die are singulated from the substrate. Other aspects and implementations are contemplated.

Abstract: In a manufacturing method of an image sensor, a lightproof film (an antireflective film for avoiding flares) is formed over a wiring area; a transparent film is formed over an imaging area using a material capable of patterning; a transparent film, for forming micro lense on top, is formed on the transparent film, wherein a height of the top surfaces of the transparent film and the lightproof film are evenly formed.

Abstract: An electrical circuit is formed by forming and patterning a conductive layer on a substrate, forming and patterning a conductive layer on another substrate, depositing a dielectric layer on at least a portion of one of conductive layers, mounting an integrated circuit (IC) between the substrates, coupling the IC to the conductive layers, and affixing the substrates together with the conductive layers between the substrates. These are either separate substrates or a unitary substrate. The IC is mounted either to a substrate, a conductive layer, or a dielectric layer. The IC is coupled to the conductive layers either directly or through openings formed in the dielectric layer. An interior conductive layer may be used to couple the IC to the conductive layers.

Abstract: Disclosed is a method of making a mold lock for bonding leadframe-to-plastic in an IC package. Steps include providing niches from opposing sides of the leadframe. The opposing niches are arranged such that an aperture and a mechanical key are formed within the leadframe material by the partial intersection of the niches. The key is encapsulated with mold compound to form a lock. An IC package mold lock in a leadframe is also disclosed, the lock having an aperture, a key, and mold compound encapsulating the key. Additionally, an IC package employing the leadframe-to-plastic lock is disclosed.

Abstract: A semiconductor device includes: a substrate on which is formed an interconnecting pattern; a first semiconductor chip provided above the substrate and having a first electrode on a surface facing the substrate; and a second semiconductor chip provided above the first semiconductor chip and having a second electrode on a surface facing the substrate. The substrate has a bent portion inclined from the first electrode to the second electrode. The interconnecting pattern extends along the bent portion and electrically connected to the first and second electrodes.

Abstract: Disclosed is an electronic device comprising a semiconductor chip including an integrated circuit having at least one electrostatic discharge sensitive device and a non-semiconductor chip, positioned in close proximity to the semiconductor chip, the non-semiconductor chip having at least one electrostatic discharge protection device. The electrostatic discharge protection device is electrically connected to the electrostatic discharge sensitive device.

Abstract: A stereolithographic method of applying material to form a protective layer on a preformed semiconductor die with a high degree of precision, either in the wafer stage, when attached to a lead frame, or to a singulated, bare die. The method is computerized and may utilize a machine vision feature to provide precise die-specific alignment. A semiconductor die may be provided with a protective structure in the form of at least one layer or segment of dielectric material having a controlled thickness or depth and a very precise boundary. The layer or segment may include precisely sized, shaped and located apertures through which conductive terminals, such as bond pads, on the surface of the die may be accessed. A plurality of discrete protective structures may be formed on corresponding semiconductor devices that are carried by a large-scale semiconductor substrate. Dielectric material may also be employed as a structure to mechanically reinforce the die-to-lead frame attachment.

Abstract: It is an object of the present invention to provide a semiconductor device capable of preventing deterioration due to penetration of moisture or oxygen, for example, a light-emitting apparatus having an organic light-emitting device that is formed over a plastic substrate, and a liquid crystal display apparatus using a plastic substrate. According to the present invention, devices formed on a glass substrate or a quartz substrate (a TFT, a light-emitting device having an organic compound, a liquid crystal device, a memory device, a thin-film diode, a pin-junction silicon photoelectric converter, a silicon resistance element, or the like) are separated from the substrate, and transferred to a plastic substrate having high thermal conductivity.

Abstract: The process includes depositing a filling material in trenches formed in at least one layer of dielectric so as to fill open pores in the dielectric. The filling material is intended to prevent the subsequent diffusion of the interconnect metal and/or of a metal of a diffusion barrier, and may be non-porous. The filling material preferably has a low dielectric constant.

Abstract: The present invention relates to a method to form an integrated device, said device comprising a first substrate and at least one element provided on a second substrate. A bonding material is arranged on at least one of said substrates. Said first and second substrates are joined together. At least one recess is provided through at least said first substrate and said material. Support structures are provided in at least a part of said at least one recess to mechanically and/or electrically interconnect said at least one element on said second substrate and said first substrate. At least one element out of said first substrate is formed to be mechanically and/or electrically connectable to said at least one support structure. At least a portion of said material between said first and second substrates is stripped away to make said element on said first substrate movable.

Abstract: A cutting method for separating individual semiconductor devices by cutting boundary portions in a group of semiconductor devices made up by arranging a plurality of semiconductor devices in which a ductile first layer and a second layer are stacked on a peripheral side thereof, the cutting method comprises a cutting step of cutting the first and second layers by moving a first rotary body from the boundary portions of the group of semiconductor devices in the direction in which the first and second layers are stacked; and a burr removal step of removing burrs from the first layer by moving a second rotary body, softer than the first rotary body and wider than the first rotary body in the direction of rotational axis, from the cut boundary portions of the group of semiconductor devices in the direction in which the first and second layers are stacked.

Abstract: The invention provides an imager having a p-n-p photodiode with an ultrashallow junction depth. A p+ junction layer of the photodiode is doped with indium to decrease transient enhanced diffusion effects, minimize fixed pattern noise and fill factor loss.

Abstract: A chip package structure is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. At least one of the chips is bonded and electrically connected to the carrier or another chip using a flip-chip bonding technique. A flip-chip bonding gap is set up between the chip and he carrier or other chips. The heat sink is set up over the top chip. The heat sink has an area bigger than the chip. The encapsulating material layer fills up the flip-chip bonding gap and covers the carrier as well as the heat sink. The encapsulating material layer is formed in a simultaneous molding process and has a thermal conductivity more than 1.2 W/m.K. Furthermore, a plurality of standoff components may be selectively positioned on the heat sink.

Abstract: In a method and system for placing an IC (integrated circuit) die onto a package substrate, a first reference is determined after locating a first fiducial on the package substrate, and a second reference is determined after locating a second fiducial on the package substrate. The IC die is placed onto the package substrate to be aligned with respect to the first and second references of the first and second fiducials that are comprised of a plurality of markings such as a plurality of dots.

Abstract: A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewall, and angularly implanting a dopant of a second conductivity into the second sidewall. The at least one mesa is converted to a pillar by diffusing the dopants into the at least one mesa. The pillar is then converted to a column by angularly implanting a dopant of the first conductivity into a first sidewall of the pillar, and by angularly implanting the dopant of the first conductivity type into a second sidewall of the pillar. The dopants are then diffused into the pillar to provide a P-N junction of the first and second doped regions located along the depth direction of the adjoining trench. Finally, the trenches are filled with an insulating material.

Abstract: Disclosed herein is a method of making integrated circuits. In one embodiment the method includes forming tungsten plugs in the integrated circuit and forming electrically conductive interconnect lines in the integrated circuit after formation of the tungsten plugs. At least one tungsten plug is electrically connected to at least one electrically conductive interconnect line. Thereafter at least one electrically conductive interconnect line is exposed to ionized air.

Abstract: A method for manufacturing an image sensor including an array of pixels and an imaging lens exit pupil for focusing rays of light onto the array of pixels is provided. Each pixel includes a light sensitive region and at least one optical element associated therewith. The method includes positioning the at least one optical element for each pixel relative to its associated light sensitive region based upon a range of acceptable angles of incidence for the rays of light from the imaging lens exit pupil.

Abstract: A process for introducing structures that have different dimensions, particularly with regard to depth, in which just one lithography level is required, is disclosed. This is achieved by use of a layer stack deposited on a substrate, where one layer in particular is used to store information related to the dimensioning of the different structures. The layer is partially opened up to expose the substrate at locations corresponding to where deep structures are to be formed. Deep structures are subsequently etched into the substrate, after which the layer is opened up at locations corresponding to where shallow structures are to be formed. The latter locations are subsequently etched to the desired depth of the shallower structures. The process can be used instead of conventional the dual damascene technology for the structuring of contact holes and interconnects.

Abstract: A method for fabricating Surface Acoustic Wave filter packages uses a package sheet having an outline pattern and anti-bur holes. In the package sheet for a Surface Acoustic Wave filter package, the outline pattern is formed along outer peripheries of chip mounting areas where a plurality of SAW filter chips are to be mounted. The outline pattern is contacted with a metal shield layer formed on the SAW filter chips and a predetermined region of the package sheet. Circular anti-bur holes are located at the corners of the chip mounting areas and on cutting lines along which the sheet is to be singulated into individual SAW filter packages.

Abstract: A method and apparatus for a backsided and recessed optical package connection is described. The method includes the formation of a substrate having a top surface layer and an opposed layer, including one or more recessed portions. Following formation of the substrate, leads of a lead unit are coupled to one or more of the recessed portions of the substrate. Next, one or more optical electronic components are mounted onto the top surface of the substrate. Once the optoelectric components are mounted to the top surface of the substrate, a cap is attached to the top surface of the substrate to encapsulate the one or more optical electronic components and form an optoelectronic package.