Patents Examined by Ly V. Hua
  • Patent number: 6009526
    Abstract: An information security system for tracing information outflow from a remotely accessible computer or computer network is disclosed. The system includes an internal communication system that has at least one internal computer for transmitting security information by tracing data through communication equipment, outputting the data to an external output means, and connecting the internal computer to an external network. A communication monitoring device stores information regarding the data that is to be transmitted by applying a security policy according to a security grade assigned to the destination to which the data is to be transmitted. The communication monitoring device is configured for extracting the identification of the destination from the transmitted data.
    Type: Grant
    Filed: September 12, 1997
    Date of Patent: December 28, 1999
    Inventor: Seung-ryeol Choi
  • Patent number: 6009525
    Abstract: Methods of electronic software distribution are provided in which software products may be wrapped by their publishers in a straightforward, secure manner, but in such a way as to allow for the addition of information by downstream distribution channel partners, e.g., distributors and merchants (resellers). Distribution policies, or business rules, governing the distribution process may be fixed by the software publisher or may be left to the discretion of channel partners. The software product itself, however, is secured against tampering or inadvertent infection by a virus. A tool facilitates the foregoing incremental wrapping process without requiring sophistication in computer technology on the part of channel partners. The publisher may use a conventional setup tool of the publisher's choice to prepare a setup file set for distribution. That is, the wrapping tool need not influence the publisher's choice of setup tools.
    Type: Grant
    Filed: August 29, 1997
    Date of Patent: December 28, 1999
    Assignee: Preview Systems, Inc.
    Inventor: Cay S. Horstmann
  • Patent number: 6009524
    Abstract: An improved system and method for FLASH BIOS upgrades which is particularly useful in network hubs. Each hub or node which is equipped with a FLASH memory is also equipped with a validation system, which ensures that a received FLASH upgrade is authorized and uncorrupted. Each set of instructions to be flashed is marked both with a vendor authorization digital signature and also a system administrator authorization digital signature, and BOTH digital signatures must be recognized by the validation system before the FLASH memory will be upgraded. Because digital signatures are used for security purposes, flash upgrades can be performed from any location on the network, and are not limited to an administrative node.
    Type: Grant
    Filed: August 29, 1997
    Date of Patent: December 28, 1999
    Assignee: Compact Computer Corp
    Inventors: Sompong P. Olarig, Michael F. Angelo
  • Patent number: 6003134
    Abstract: Multiple applications upon an IC microprocessor are protected with bi-modal CPU operation, either application or system mode, using an operation flag determining the mode and dependent upon a mode change interrupt which clears all working memory unnecessary to operation in the next mode. Access authorization setting program and data memory boundaries according to the particular custom command in comparison registers is utilized in application initialization. From application mode, data files are accessed only through a system subroutine. Request of an address beyond the territory assigned to the custom command utilized results in a hardware interrupt which clears all working memory and registers unnecessary to forward a status word indicating abnormal termination. Application completion forwards the result with a status word indicating successful completion.
    Type: Grant
    Filed: December 30, 1997
    Date of Patent: December 14, 1999
    Inventors: Chih-Cheng Kuo, Minwen Lo
  • Patent number: 6000041
    Abstract: A network interface system and related methods. A single logic control module, which may be implemented in hardware or software, is utilized to perform any of a number of data manipulation functions including, for example, parsing, filtering, data generation or analysis, based upon one or more programmably configurable protocol descriptions which may be stored in and retrieved from an associated memory.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: December 7, 1999
    Assignee: NB Networks
    Inventors: Peter D. Baker, Karen Neal
  • Patent number: 5996086
    Abstract: In a redundant server network system, failover services for a failed server are provided by a survivor server belonging to a common failover group. At startup of a local server process running on the survivor server, a context is created for the local server and for each remote server belonging to the same failover group as the local server. At startup the context of the local server is also activated. The local server process is configured to operate on and make decisions based upon activated contexts. Each context includes server specific configuration and control information. When the survivor server must provide failover services for a failed server belonging to its same failover group, the context corresponding to the failed remote server is activated.
    Type: Grant
    Filed: October 14, 1997
    Date of Patent: November 30, 1999
    Assignee: LSI Logic Corporation
    Inventors: William P. Delaney, Gerald J. Fredin, Andrew J. Spry
  • Patent number: 5996096
    Abstract: Reduced specification DRAMs are used in memory assemblies in such a way as to maximize the use of the good cells in the reduced specification DRAM chips. An external memory array is mapped to replace defective memory locations on a real time basis. The major components are (1) a non-volatile storage device, (2) a logic device, and (3) a volatile storage device. The non-volatile storage device, such as an EPROM, EEPROM, or a flash memory chip, is used to retain address information for all memory fails on a given assembly. In simpler implementations, the use of specific combinations of RAM failure types can be used in addition to a logic decode chip, with the raw card identifying to the decode chip the failing address information (via solder jumpers). The logic device is an ASIC or programmable logic device which contains the bit steering logic and timing generation logic to redirect defective RAM addresses to an alternate storage device for all read and write operations.
    Type: Grant
    Filed: November 15, 1996
    Date of Patent: November 30, 1999
    Assignee: International Business Machines Corporation
    Inventors: Timothy Jay Dell, Mark William Kellogg
  • Patent number: 5991876
    Abstract: An electronic rights management and authorization system to account for the dynamic, multi-dimensional, and granular nature of rights. A database structure divides works and rights into two related tables. A works table includes information sufficient to identify works managed by the system, while a rights table identifies a right associated with a work and includes one or more date fields delimiting the right. The rights table may also include type of use information. Additional tables, such as a work relation table, a party table, or an order table, may be provided. Software is used to manage and to query the database structure. The system has broad applicability to intellectual, real, and personal property; contract management; and similar items. The system may be implemented in standalone mode, through the client/server model of computing, or over the Internet.
    Type: Grant
    Filed: April 1, 1996
    Date of Patent: November 23, 1999
    Assignee: Copyright Clearance Center, Inc.
    Inventors: Woodrow W. Johnson, Christine J. Atkins, Jon Yoh
  • Patent number: 5987623
    Abstract: A memory module comprises a plurality of memory chips, data input/output terminals, and switching means. One word in a memory chip comprises a plurality of bits, and each memory chip includes a number of input/output terminals corresponding to one word. The number of data input/output terminals is less than the total number of input/output terminals of the memory chips. Switching means switches a connection between input/output terminals of the memory chips and data input/output terminals. Only those input/output terminals of the memory chips which are connected to non-defective bits are connected to the data input/output terminals.
    Type: Grant
    Filed: March 26, 1997
    Date of Patent: November 16, 1999
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yoichi Ushida
  • Patent number: 5987610
    Abstract: A virus screening method includes steps of routing a call between a calling party and a called party of a telephone network, receiving computer data from a first party of the calling party and the called party, and detecting a virus in the computer data. In response to detecting the virus, a step of inhibiting communication of at least a portion the computer data to a second party of the calling party and the called party is performed. A virus screening system is also disclosed.
    Type: Grant
    Filed: February 12, 1998
    Date of Patent: November 16, 1999
    Assignee: Ameritech Corporation
    Inventors: Edward J. Franczek, John Thomas Bretscher, Raymond Walden Bennett, III
  • Patent number: 5987626
    Abstract: The precise detection of errors in computer programs using the hardware watchpoint mechanism found in computers is disclosed. In one embodiment, a software detection phase of a method detects the approximate location of an error, generating information regarding this approximate location. In this embodiment, a hardware watchpoint phase of the method detects the precise location of the error based on the information generated by the software detection phase, generating information regarding the precise location. Finally, in this embodiment of the invention, a debugger phase of the method identifies the statement in the computer program causing the error, based on the information generated by the hardware watchpoint phase.
    Type: Grant
    Filed: August 25, 1997
    Date of Patent: November 16, 1999
    Assignee: Cray Research, Inc.
    Inventor: Terry D. Greyzck
  • Patent number: 5987606
    Abstract: A method and system for filtering Internet content retrieved from an Internet computer network (110) by a remote Internet Service Provider ("ISP") server (100) and forwarded to a local client computer (10). The method and system matches at least one filtering scheme (121), such as an inclusive or exclusive filter, and at least one set of filtering elements (120), such as a list of allowed or excluded sites, to each Internet access request generated at the local client computer (10). The filtering scheme is implemented on the ISP server (100).
    Type: Grant
    Filed: March 19, 1997
    Date of Patent: November 16, 1999
    Assignee: Bascom Global Internet Services, Inc.
    Inventors: Peter Cirasole, Robert DeRosa, Robert Fox
  • Patent number: 5983349
    Abstract: A changer apparatus capable of providing security protection. Tape cassettes are selected from a plurality of compartments constituting a cassette rack, and are loaded into drives (102-1) through (102-P) which write and read data to and from the cassettes. A nonvolatile memory (114) stores information about security protection locked on elements such as the compartments of the medium rack and the drives. When security protection is to be locked, a controller (110) admits an externally input security protection locking command, and writes accordingly to the memory (114) security protection information representing, for example, host IDs, password numbers, security levels, and a group of elements of which security is to be protected. When security protection is to be unlocked, the controller (110) admits an externally input security protection unlocking command, and erases the security protection information accordingly from the memory (114).
    Type: Grant
    Filed: March 5, 1998
    Date of Patent: November 9, 1999
    Assignee: Sony Corporation
    Inventors: Masahiro Kodama, Yoshitsugu Taki
  • Patent number: 5978935
    Abstract: A dual-port RAM-type ring-address FIFO including a data input register with a set of transparent latches is tested by causing the FIFO to execute a test method comprised of a set of interwoven steps. Upon execution, the steps of the method cause the FIFO to manifest all possible memory, address and functional faults. This test method manifests faults by causing the FIFO to alter the state of various flags it normally sets and by altering the logic state of the data normally produced by the FIFO.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: November 2, 1999
    Inventors: Ilyoung Kim, Larry Ray Fenstermaker, Yervant Zorian
  • Patent number: 5978938
    Abstract: In a data processing system including a bus connected to a plurality of devices capable of driving said bus, error reporting and isolation is achieved by signaling a self-check to each device connected to the bus to determine if it was driving the bus at the time an error occurred. The bus check request is generated by one of the devices connected to the bus in response to detecting either a parity error or an internal error. If a parity error is detected, a bus check request is signaled to a combining unit connected to the bus. The combining unit signals the self-check to each of the devices attached to the bus in response to receiving the bus check request. Each device determines whether it was driving the bus at the time the error occurred and, if so, sets a source of error indicator on the device. Similarly, if an internal error is detected, the detecting device sets source of error and internal error indicators on the detecting device and signals a bus check request to the combining unit.
    Type: Grant
    Filed: November 19, 1996
    Date of Patent: November 2, 1999
    Assignee: International Business Machines Corporation
    Inventors: John M. Kaiser, Warren E. Maule
  • Patent number: 5974550
    Abstract: Authenticating a remote process operating in an address space different than that of a local process includes the steps of creating, by the local process, a tamper resistant module containing a temporary secret, sending the tamper resistant module and a challenge from the local process to the remote process, executing the tamper resistant module by the remote process and recovering the secret when the integrity of the remote process is verified by the tamper resistant module, encoding the challenge using the secret to produce a response, sending the response to the local process, and decoding the response by the local process. Optionally, the tamper resistant module includes a request for information from the second process and the response includes the answer to the request for information.
    Type: Grant
    Filed: December 12, 1997
    Date of Patent: October 26, 1999
    Assignee: Intel Corporation
    Inventor: Richard L. Maliszewski
  • Patent number: 5968176
    Abstract: A system provides for establishing security in a network that include nodes having security functions operating in multiple protocol layers. Multiple network devices, such as remote access equipment, routers, switches, repeaters and network cards having security functions are configured to contribute to implementation of distributed firewall functions in the network. By distributing firewall functionality throughout many layers of the network in a variety of network devices, a pervasive firewall is implemented. The pervasive, multilayer firewall includes a policy definition component that accepts policy data that defines how the firewall should behave. The policy definition component can be a centralized component, or a component that is distributed over the network. The multilayer firewall also includes a collection of network devices that are used to enforce the defined policy.
    Type: Grant
    Filed: May 29, 1997
    Date of Patent: October 19, 1999
    Assignee: 3Com Corporation
    Inventors: Danny M. Nessett, William Paul Sherer
  • Patent number: 5968184
    Abstract: A method and appartus maintain a disk drive system in a more reliable and simplified manner. Maintenance commands directed to logical volumes of the physical disk drive units are configured to apply to the entire physical disk drive unit so that a maintenance command need not be repeated for each logical volume to be affected. Should a failure be received with regard to any one or more logical volumes, the apparatus and method repeat the maintenance command, but only for those failed logical volumes. The maintenance command can also be applied to a group of physical devices using this procedure.
    Type: Grant
    Filed: June 3, 1997
    Date of Patent: October 19, 1999
    Assignee: EMC Corporation
    Inventor: Ishai Kedem
  • Patent number: 5961645
    Abstract: Multiple approaches are used with a filter to handle naming ambiguities when requesting access to a plurality of network resources through a public network such as the Internet. One approach is to consider responses from the public network as well as requested URLs in determining whether to allow or deny resources. The response information used may include header information or the resource itself. If the header information includes a new URL, the new URL can be forwarded to the requestor, or submitted to the public network. A permission database is queried to determine whether a resource corresponding to the new URL should be forwarded to the requestor. A checksum database can also be used to determine if a specific resource should be forwarded to the requestor. Another approach is to record and maintain a database of aliases for URLs. When a URL is requested, the alias URLs are determined for that URL.
    Type: Grant
    Filed: October 1, 1996
    Date of Patent: October 5, 1999
    Assignee: AT&T Corp.
    Inventor: Brenda Sue Baker
  • Patent number: 5961650
    Abstract: A user definable set of event rollup relationships are maintained as a configuration element. Transitive closure of event rollup relationships is checked at the time of specification to detect cycles and prevent runtime errors. When an event to be processed is detected, the event is compared to defined rollup relationships and queued events to determined if the detected event may be rolled up into at least one queued event or vice versa. If the detected event may be rolled up into a queued event, the detected event is not queued. When any of the queued event may be rolled up into the detected event, the queued events are deleted if processing has not already begun.
    Type: Grant
    Filed: July 9, 1997
    Date of Patent: October 5, 1999
    Assignee: International Business Machines Corporation
    Inventors: James W. Arendt, Rodolfo Augusto Mancisidor, Jayashree Ramanathan