Abstract: A network authentication system provides verification of the identity or other attributes of a network user to conduct a transaction, access data or avail themselves of other resources. The user is presented with a hierarchy of queries based on wallet-type (basic identification) and non-wallet type (more private) information designed to ensure the identity of the user and prevent fraud, false negatives and other undesirable results. A preprocessing stage may be employed to ensure correct formatting of the input information and clean up routine mistakes (such as missing digits, typos, etc.) that might otherwise halt the transaction. Queries can be presented in interactive, batch processed, or other format. The authenticator can be configured to require differing levels of input or award differing levels of authentication according to security criteria.

Abstract: Systems and methods for remotely monitoring the execution of computer programs are provided. Monitoring instructions are added the computer program so that during execution of the program, data may be collected regarding the program execution. The collected data may be automatically sent to a remote system or site for analysis. The monitoring instructions create little or no performance impact on the client yet provide valuable information to the developer of the program. Additionally, the monitoring instructions may be changes during computer program development.

Abstract: A test point selection method for scan-based built-in self-test (BIST). The method calculates a hybrid cost reduction (HCR) value as an estimated value of the corresponding actual cost reduction for all nodes in a circuit under test. A test point is then selected having a largest HCR. This iterative process continues until the fault coverage of the circuit under test reaches a desired value or the number of test points selected is equal to a maximum number of test points. In an alternative embodiment, the cost reduction factor is calculated for all nodes in the circuit under test, the HCR is calculated for only a selected set of candidates, and the candidate having the largest HCR is selected as the test point. The test point selection method achieves higher fault coverage results and reduces computational processing relative to conventional selection methods.

Abstract: Object-code instruction traces are employed to analyze selected instructions of an application program for possible failure when confronted by a year-2000 date. The analysis includes directly identifying one or more instructions of the application program that may fail, as well as identifying whether the one or more instructions have a characteristic of a predefined false-positive failure pattern. A failure-pattern descriptor is assigned to each examined instruction which is indicative of whether the instruction may fail when confronted by a date in the year-2000 range, and whether the instruction is a possible false-positive failing instruction. The analysis employs user-specifiable run-control values, as well as predetermined filter-specification values in comparing traces of each selected object-code instruction to predefined instruction failure patterns.

Abstract: According to one embodiment a transaction processing system includes a first system controller and a second system controller coupled to the first system controller. The transaction processing system further includes a second multi-media system coupled to the second system controller. While the transaction processing system is operating in a normal mode, transactions are transmitted by the first multi-media system. Furthermore, transactions are received by both the first and second multi-media system.

Abstract: A microcomputer (10) is proposed, which includes a central processing unit (11), a non-volatile memory (13), a volatile memory (14), a monitoring circuit (12) and also an input/output unit (16). Two different operating states are possible in the microcomputer (10). In the first operating state, the microcomputer executes a program which is located in the non-volatile memory (13). In the second operating state, the microcomputer (10) executes a program which is located in the volatile memory (14). The monitoring circuit (12) effects a resetting of the microcomputer (10) whenever it does not receive a monitoring signal for a predetermined time (watchdog timer). The microcomputer is distinguished in that it includes an element for suppressing monitoring signals which are always active whenever the microcomputer (10) is operating in the second operating state.

Abstract: An information accessing method permits the user data belonging to a client-server system to be accessed by a user belonging to the other client-server system under proper security and controls the permission for accessing the user data according to the security ranks of the user to be accessed and the user who wants to access the data. When a client unit issues a request for accessing the user data of the user belonging to the other client-server system, the request for access is sent to an ID conversion unit through a user ID management unit. The ID conversion unit operates to convert a user ID into a guest ID by referring to an ID conversion table and then send the request for access to a user ID management unit. The user ID management unit makes sure that the guest ID is registered by referring to the user ID table.

Abstract: Reliably detecting malfunction of an abnormality-monitoring circuit during operation of a processing unit. An electronic control unit provided with a CPU level-inverts and outputs an actuating signal during each iteration of a base routine. An abnormality-monitoring circuit clocks a fall interval of the actuating signal as charging voltage of a gradually discharged capacitor, and outputs a reset signal to the CPU when this charging voltage falls to a defined value. When a check-starting condition is fulfilled, the CPU inhibits a subsequent level inversion of the actuating signal until a predetermined time elapses after a prior level inversion. When the signal inhibition is canceled, when the charging voltage VC of the capacitor is not within a reference range (VL-VH), the CPU determines the abnormality-monitoring circuit to have malfunctioned.

Abstract: A method for determining the default operating mode of a code segment by determining whether an instruction modifies bits in both the upper-order and lower-order halves of a register. A register is set to a known value and an instruction which operates on the register is subsequently executed. After execution of the instruction, it is determined whether the high-order bits of the register have been modified by the instruction. If the instruction modifies the high-order bits of the register, a first default mode is indicated and, if the instruction does not modify the high-order bits of the register, a second default mode is indicated.

Abstract: A SCSI device available for breakdown prediction and self-examination or a breakdown prediction and self-examination method by this device which increases the overall system performance through reducing the loading of a master I2C processor and SCSI bus, by reporting to the master I2C processor only when necessary, after an I2C processor reads the status of the SCSI device.

Abstract: A program is executed on a first computer. In response to an error being detected in the execution of the program, the computer automatically retrieves revision code stored on another computer to revise the program.

Abstract: A method and apparatus for authenticating users. Prior art mechanisms require each individual application (running on an “application server”) that the user is accessing to provide for the ability to use the various authentication mechanisms. One or more embodiments of the invention externalize the authentication mechanism from the application in the form of a login server. Only the login server needs to be configured to handle authentication mechanisms. The application server checks if a request has an active and valid session (e.g., a valid session may exist when there is active communication between a client and server that has not expired). If there is not a valid session, the application server redirects the user to the login server. The login server attempts to authenticate the user using any desired authentication mechanism. Once authenticated, the login server redirects the user back to the application server.

Abstract: A wireless electronic commerce system (10) comprising a wireless gateway (18) to a wireless network (19) with which a wireless device (11) having a unique client identifier (ID) is capable of communicating. A server (15) or servers (15 and 16) is/are coupleable to the wireless gateway, delivering content items (e.g. software products) to the wireless device (11) and maintaining digital content certificates for content items and digital license certificates for licenses for the content items. The server maintains, for each wireless client associated with the system, a record of licenses for that client and a record of content items associated with each license.

Abstract: A secured network system comprising a readykey controller which has a first card reader and a power relay switch connected thereto. The user of the system inserts a microchip embedded card into the first card reader which then transmits an authorization signal to the readykey controller. The readykey controller then activates a power relay switch affixed to the computer which connects the computer's power supply to an external power source activating the computer. The secured network system also has a data relay switch which includes a manual A/B secured network switch. The manual A/B switch allows the user to receive and process classified data, by setting the switch to a predetermined position which connects a secured network server to the computer. The user inserts his proximity card into a second card reader which transmits a second authorization signal to the readykey controller. The readykey controller, responsive to the second authorization signal, activates the data relay switch.

Abstract: A computer program device and a computer program product are introduced comprising a computer storage debugging device readable by a digital processing apparatus; and a debugging program means is introduced. The debugging program means is to be used with the program storage device and includes instructions executable by the digital processing apparatus for performing method steps for debugging a particular transaction in a computer network environment, where the environment includes a plurality of clients in processing communication with one another. The method steps comprise: identifying at least one client present in said environment and storing pertinent information about any identified clients; providing information about whether or not a particular session needs to be debugged; and determining if a particular session needs debugging so that debugging operation can be started accordingly.

Abstract: A computer system has a plurality of processing units (2-1,2-2,2-n) connected via one or more system buses (1-1,1-2). Each processing unit (2-1,2-2,2-n) has three or more processors (20-1,20-2,20-3) on a common support board (PL) and controlled by a common clock unit (1000). The three processors (20-1,20-2,20-3) perform the same operation and a fault in a processor (20-1,20-2, 20-3) is detected by comparison of the operations of the three processors (20-1,20-2,20-3). If one processor (20-1,20-2,20-3) fails, the operation can continue in the other two processors (20-1,20-2,20-3) of the processing unit (2-1,2-2,2-n), at least temporarily, before replacement of the entire processing unit (2-1,2-2, 2-n). Furthermore, the processing unit (2-1,2-2,2-n) may have a plurality of clocks (A,B) within the clock unit (1000), with a switching arrangement so that the processors (20-1,20-2,20-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails.

Abstract: A method and implementing system are provided for handling detected faults in a processor to improve reliability of a computer system. An exemplary fault-tolerant on-line transactional (OLT) computer system is illustrated which includes first and second OLT processors connected to an I/O processor through a system bus. Transaction results are stored in local processor buffers and at predetermined batch intervals, the stored transactions are compared. The matched transaction results are flushed to data store while unmatched transactions are re-executed. If the same errors do not occur during a re-execution, the errors are determined to be transient and the transaction results are flushed to storage.

Abstract: A method and apparatus for reverting a disk drive to an earlier point in time is disclosed. Changes made to the drive are saved in a circular history buffer which includes the old data, the time it was replaced by new data, and the original location of the data. The circular history buffer may also be implemented by saving new data elements into new locations and leaving the old data elements in their original locations. References to the new data elements are mapped to the new location. The disk drive is reverted to an earlier point in time by replacing the new data elements with the original data elements retrieved from the history buffer, or in the case of the other embodiment, reads to the disk are mapped to the old data elements stilled stored in their original locations. The method and apparatus may be implemented as part of an operating system, or as a separate program, or in the controller for the disk drive. The method and apparatus are applicable to other forms of data storage as well.

Abstract: A computer management system includes an agent connected to a computer to be managed for executing instructions on the computer to be managed, a service processor board having a processor independent from the computer to be managed for monitoring fault in the computer to be managed and controlling power of the computer to be managed, a manager for executing instructions on a management computer and conducting controls such as fault monitoring and power control through the agent over a network including a public line, and a service processor manager directly connected to the service processor for conducting remote power-on and receiving and diagnosing critical fault. The service processor and the service processor manager are provided with switching circuits for switching an asynchronous interface for remotely connecting to the computer to be managed and an asynchronous interface for directly connecting to a local processor of the service processor.

Abstract: A computer password security method employing a south bridge circuitry where the user password is compared to a secured password stored in secured memory which is directly accessible to the south bridge circuitry, removing any threat of data bus and/or unprotected memory snooping.