Patents Examined by Lynne Gurley
  • Light emitting device, electrode structure, light emitting device package, and lighting system
    Patent number: 8723203
    Abstract: Provided are a light emitting device, an electrode structure, a light emitting device package, and a lighting system. The light emitting device includes a conductive layer, an electrode, a light emitting structure layer disposed between the electrode and the conductive layer and comprising a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, and a light guide layer between the first semiconductor layer and the electrode.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: May 13, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: Kwang Ki Choi, Hwan Hee Jeong, Sang Youl Lee, June O Song
  • Device chip carriers, modules, and methods of forming thereof
    Patent number: 8710523
    Abstract: The present invention provides novel methods of forming component carriers, component modules, and the carriers and modules formed therefrom which utilize thick film technology. In some embodiments, these methods are used to form lighting device chip carriers and modules. In further embodiments, these lighting device chip carriers and modules are used in LED applications.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: April 29, 2014
    Assignee: E I du Pont de Nemours and Company
    Inventors: Joel Slutsky, Brian D. Veeder, Thomas Lin
  • Socket type MEMS device with stand-off portion
    Patent number: 8710638
    Abstract: A method for fabricating an integrated circuit device is disclosed. The method includes providing a first substrate; bonding a second substrate to the first substrate, the second substrate including a microelectromechanical system (MEMS) device; and bonding a third substrate to the first substrate.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: April 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ting-Hua Wu
  • Device for and a method of processing data
    Patent number: 8675880
    Abstract: A device (100) for processing data, the device (100) comprising a detection unit (110) adapted for detecting individual reproduction modes indicative of a manner of reproducing the data separately for each of a plurality of human users, and a processing unit (120) adapted for processing the data to thereby generate reproducible data separately for each of the plurality of human users in accordance with the detected individual reproduction modes.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: March 18, 2014
    Assignee: Koninklijke Philips N.V.
    Inventors: Werner Paulus Josephus De Bruijn, Daniel Willem Elisabeth Schobben, Willem Franciscus Johannes Hoogenstraaten, Ronaldus Maria Aarts, Johannes Hermannus Streng
  • Semiconductor light emitting diode
    Patent number: 8659039
    Abstract: A highly-efficient semiconductor light emitting diode with improved light extraction efficiency comprising at least a substrate having a plurality of crystal planes, a first conductivity-type barrier layer, an active layer serving as a light emitting layer and a second conductivity-type barrier layer stacked on the substrate. The semiconductor light emitting diode comprises a ridge structure configured from one flat surface and at least two inclining surfaces in the in-plane direction. The width (W) of the flat surface of the ridge structure is 2? (?: light emission wavelength) or less.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: February 25, 2014
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Xuelun Wang, Mutsuo Ogura
  • Semiconductor light emitting device
    Patent number: 8653498
    Abstract: According to one embodiment, a semiconductor light emitting device includes: a stacked structural body, a first electrode; and a second electrode. The stacked structural body includes a first semiconductor layer of n-type, a second semiconductor layer of p-type, and a light emitting portion provided therebetween. The first electrode includes a first contact electrode portion. The second electrode includes a second contact electrode portion and a p-side pad electrode. A sheet resistance of the second contact electrode portion is lower than a sheet resistance of the first semiconductor layer. The p-side pad electrode is provided farther inward than a circumscribed rectangle of the first contact electrode portion, and the first contact electrode portion is provided farther outward than a circumscribed rectangle of the p-side pad electrode.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: February 18, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeya Kimura, Taisuke Sato, Toshihide Ito, Takahiro Sato, Toshiyuki Oka, Shinya Nunoue
  • Dual vertical channel transistor and fabrication method thereof
    Patent number: 8653584
    Abstract: A dual vertical channel transistor includes a tuning fork-shaped substrate body; a buried bit line embedded at a bottom of a recess between two prong portions of the tuning fork-shaped substrate body; an out-diffused drain region adjacent to the buried bit line in the tuning fork-shaped substrate body; a source region situated at a top portion of each of the two prong portions of the tuning fork-shaped substrate body; an epitaxial portion connecting the two prong portions of the tuning fork-shaped substrate body between the out-diffused drain region and the source region; a front gate situated on a first side surface of the tuning fork-shaped substrate body; and a back gate situated on a second side surface opposite to the first side surface of the tuning fork-shaped substrate body.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: February 18, 2014
    Assignee: Nanya Technology Corp.
    Inventor: Shing-Hwa Renn
  • Semiconductor device with multilayer wiring structure formed within and method of manufacturing the same
    Patent number: 8618657
    Abstract: A semiconductor device includes a semiconductor chip of a multilayer wiring structure having an insulating film formed on a surface thereof, multiple electrode pads formed at a central part and an outer peripheral part of the insulating film, and multiple protective metal layers formed respectively on the electrode pads. The semiconductor device also includes a substrate having the semiconductor chip mounted thereon and including multiple substrate terminals formed on a surface thereof respectively in positions corresponding to the electrode pads. The semiconductor chip is mounted on the substrate by connecting a stud bump to a solder bump. The stud bump is formed on any one of each of the protective metal layers and each of the substrate terminals and the solder bump is formed on the other one of each of the protective metal layers and each of the substrate terminals.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: December 31, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiichiro Higaki, Koichi Sugihara, Katsuya Murakami, Shigenori Sawachi, Mitsuru Oida
  • Utilization of organic buffer layer to fabricate high performance carbon nanoelectronic devices
    Patent number: 8614141
    Abstract: A fabrication process for a nanoelectronic device and a device are provided. Channel material is deposited on a substrate to form a channel. A source metal contact and a drain metal contact are deposited on the channel material, and the source metal contact and the drain metal contact are on opposing ends of the channel material. A polyhydroxystyrene derivative is deposited on the channel material. A top gate oxide is deposited on the polymer layer. A top gate metal is deposited on the top gate oxide.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: December 24, 2013
    Assignee: International Business Machines Corporation
    Inventors: Phaedon Avouris, Damon B. Farmer, Fengnian Xia
  • Utilization of organic buffer layer to fabricate high performance carbon nanoelectronic devices
    Patent number: 8614435
    Abstract: A fabrication process for a nanoelectronic device and a device are provided. Channel material is deposited on a substrate to form a channel. A source metal contact and a drain metal contact are deposited on the channel material, and the source metal contact and the drain metal contact are on opposing ends of the channel material. A polyhydroxystyrene derivative is deposited on the channel material. A top gate oxide is deposited on the polymer layer. A top gate metal is deposited on the top gate oxide.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: December 24, 2013
    Assignee: International Business Machines Corporation
    Inventors: Phaedon Avouris, Damon B. Farmer, Fengnian Xia
  • Thin film transistor method of fabricating the same
    Patent number: 8610128
    Abstract: A thin film transistor includes: a silicon nanowire on a substrate, the silicon nanowire having a central portion and both side portions of the central portion; a gate electrode on the central portion; and a source electrode and a drain electrode spaced apart from the source electrode on the both side portions, the source electrode and the drain electrode electrically connected to the silicon nanowire, respectively.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: December 17, 2013
    Assignee: LG Display Co., Ltd.
    Inventors: Gee-Sung Chae, Mi-Kyung Park
  • Semiconductor electroluminescent device with a multiple-quantum well layer formed therein
    Patent number: 8610105
    Abstract: Provided is a semiconductor electroluminescent device with an InGaAlAs-based well layer having tensile strain, or a semiconductor electroluminescent device with an InGaAsP-based well layer having tensile strain and with an InGaAlAs-based barrier layer which is high-performance and highly reliable in a wide temperature range. In a multiple-quantum well layer of the semiconductor electroluminescent device, a magnitude of interface strain at an interface between the well layer and the barrier layer is smaller than a magnitude of critical interface strain determined by a layer thickness value which is larger one of a thickness of the well layer and a thickness of the barrier layer.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: December 17, 2013
    Assignee: Oclaro Japan, Inc.
    Inventors: Toshihiko Fukamachi, Takashi Shiota, Takeshi Kitatani, Nozomu Yasuhara, Atsushi Nakamura, Mitsuhiro Sawada
  • Resistive heating device for fabrication of nanostructures
    Patent number: 8592732
    Abstract: Apparatuses and techniques relating to a resistive heating device are provided.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: November 26, 2013
    Assignee: Korea University Research and Business Foundation
    Inventor: Kwangyeol Lee
  • Semiconductor device comprising an electromagnetic waveguide
    Patent number: 8581412
    Abstract: A semiconductor device includes a substrate. On at least one face of that substrate, integrated circuits are formed. At least one electromagnetic waveguide is also included, that waveguide including two metal plates that are placed on either side of at least one part of the thickness of the substrate and are located facing each other. Two longitudinal walls are placed facing each other and are formed by metal vias made in holes passing through the substrate in its thickness direction. The metal vias electrically connect the two metal plates.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: November 12, 2013
    Assignee: STMicroelectronics S.A.
    Inventors: Romain Pilard, Daniel Gloria, Frederic Gianesello, Cedric Durand
  • Organic field effect transistor
    Patent number: 8569746
    Abstract: An organic field effect transistor including an organic semiconductor layer constituting a current path between a source electrode and a drain electrode wherein the organic semiconductor layer is made of a conjugated polymer having a depletion layer and a conductivity of the organic semiconductor layer is controlled by using a gate electrode, wherein the depletion layer is formed by joining a reductive material being capable of forming Schottky contact with the organic semiconductor layer made of the conjugated polymer. There can be provided an organic field effect transistor using a conjugated polymer as an organic semiconductor and being capable of maintaining an insulation property.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: October 29, 2013
    Assignee: Kyushu Institute of Technology
    Inventors: Shuichi Nagamatsu, Wataru Takashima, Keiichi Kaneto
  • Power semiconductor devices having selectively doped JFET regions and related methods of forming such devices
    Patent number: 8563986
    Abstract: Semiconductor switching devices include a wide band-gap drift layer having a first conductivity type (e.g., n-type), and first and second wide band-gap well regions having a second conductivity type (e.g., p-type) on the wide band-gap drift layer. First and second wide band-gap source/drain regions of the first conductivity type are on the first and second wide band-gap well regions, respectively. A wide band-gap JFET region having the first conductivity type is provided between the first and second well regions. This JFET region includes a first local JFET region that is adjacent a side surface of the first well region and a second local JFET region that is adjacent a side surface of the second well region. The local JFET regions have doping concentrations that exceed a doping concentration of a central portion of the JFET region that is between the first and second local JFET regions of the JFET region.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: October 22, 2013
    Assignee: Cree, Inc.
    Inventor: Qingchun Zhang
  • STT MRAM magnetic tunnel junction architecture and integration
    Patent number: 8564079
    Abstract: A magnetic tunnel junction (MTJ) device for a magnetic random access memory (MRAM) in a semiconductor back-end-of-line (BEOL) process flow includes a first metal interconnect for communicating with at least one control device and a first electrode for coupling to the first metal interconnect through a via formed in a dielectric passivation barrier using a first mask. The device also includes an MTJ stack for storing data coupled to the first electrode, a portion of the MTJ stack having lateral dimensions based upon a second mask. The portion defined by the second mask is over the contact via. A second electrode is coupled to the MTJ stack and also has a same lateral dimension as defined by the second mask. The first electrode and a portion of the MTJ stack are defined by a third mask. A second metal interconnect is coupled to the second electrode and at least one other control device.
    Type: Grant
    Filed: January 19, 2009
    Date of Patent: October 22, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Seung H. Kang, Xia Li, Shiqun Gu, Kangho Lee, Xiaochun Zhu
  • Audio processing apparatus and method of mobile device
    Patent number: 8542839
    Abstract: An audio processing apparatus and method for a mobile device are provided. The audio processing apparatus and method may appropriately determine sound source localizations corresponding to a voice signal and an audio signal, and thereby may simultaneously provide a voice call service and a multimedia service. Also, the audio processing apparatus and method may guarantee quality of the voice call service even when simultaneously providing the voice call service and the multimedia service.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: September 24, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang Yong Son, Do Hyung Kim, Sang Oak Woo, Kang Eun Lee
  • Method for making a semi-conducting substrate located on an insulation layer
    Patent number: 8536027
    Abstract: A method for making a silicon layer extending on an insulation layer, including the steps of forming a silicon-germanium layer on at least a portion of a silicon wafer; transforming portions of the silicon-germanium layer into porous silicon pads; growing a monocrystalline silicon layer on the silicon-germanium layer and on the porous silicon pads; removing the silicon-germanium layer; oxidizing the porous silicon pads; and depositing an insulation material on the silicon layer.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: September 17, 2013
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Aomar Halimaoui, Daniel Bensahel
  • Process of forming an electronic device including a conductive stud over a bonding pad region
    Patent number: 8530346
    Abstract: An electronic device can include an interconnect level including a bonding pad region. An insulating layer can overlie the interconnect level and include an opening over the bonding pad region. In one embodiment, a conductive stud can lie within the opening and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer lying along a side and a bottom of the opening and a conductive stud lying within the opening. The conductive stud can substantially fill the opening. A majority of the conductive stud can lie within the opening. In still another embodiment, a process for forming an electronic device can include forming a conductive stud within the opening wherein from a top view, the conductive stud lies substantially completely within the opening. The process can also include forming a second barrier layer overlying the conductive stud.
    Type: Grant
    Filed: October 11, 2010
    Date of Patent: September 10, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Lakshmi N. Ramanathan, Tien Yu T. Lee, Jinbang Tang