Abstract: There is disclosed a method for reducing leakage current of an LSI, which enables information not memory-mapped in the address of a CPU to be easily saved, and information saving and returning to be carried out by simple switching operations without needing any special switching operations by the CPU. An LSI chip is divided into two parts, namely a main power supply region and a backup power supply region. A scan path is provided to interconnect memory units including a CPU, a CPU peripheral circuit and so on, in the main power supply region. When an operation standby state is set, a scanning operation through the scan path is started, information held in the memory units of each of the circuits in the main power supply region is read, and then thus read information is saved in an storage section in the backup power supply region.

Abstract: A host-side wireless interface services communications between a wireless user input device and a serviced host. The host-side wireless interface includes a wireless network interface, a host interface, and may include additional components. The wireless network interface wirelessly communicates with the wireless user input device. The host interface communicatively couples to the wireless interface and to the serviced host. When the serviced host initiates bootstrap operations via a Basic Input/Output System (BIOS), the host interface operates in a BIOS host interface mode to allow input from the wireless user input device to the BIOS during the bootstrap operations. Further, when the serviced host initiates Operating System (OS) operations, the host interface operates in an OS host interface mode, wherein the OS host interface mode differs from the BIOS host interface mode.

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes an integrated circuits (IC), a power supply that supplies power to the IC and an over-current protection (OCP) circuit. The OCP circuit prevents the exceeding a predetermined power threshold during a short circuit condition while the IC is enabled to receive a greater power level.

Abstract: A high-performance and miniaturizable duplexed processor system is provided. In communications between respective corresponding processor units on 0- and 1-system processor cards C0 and C1, a sequence number is added to transmission data to assess the continuity of the transmission data, and to thereby retransmit missing data. Also, in communications between processor units on the same processor card, interprocessor connection units PC0 and PC1 autonomously transfer data. Furthermore, each processor card is equipped with an input/output unit (an input/output switching unit and an input/output interface unit), so that each input/output switching unit IC0 and IC1 switches input data paths according to operating states of the processor card equipped therewith.

Abstract: A method of sequentially selecting a bootable memory module for booting is disclosed, wherein memory modules are detected in sequence to choose usable memory modules before loading various parameters stored in a BIOS of a computer into the memory modules inserted into a memory module slot of a main board of the computer. The various parameters of the BIOS are then loaded into a first memory module of the usable memory modules. Thereafter, the parameters stored in the first memory module are compared with the original parameters of the BIOS to determine whether they are matched. If they are matched, a subsequent booting operation is then performed. If they are not matched, the comparing step is continuously performed in sequence until a bootable memory module is found.

Abstract: This invention (The Customer Contact Channel Changer) enables the integration of different Customer Contact Channels such as live call center ACD (Automatic Call Distribution) agents, ADSI (Analog Display Services Interface) enhanced IVR (Interactive Voice Response) systems and WWW (World Wide Web ) servers. The world wide web servers are used to allow customers with computer equipment to access information from an organizations databases in a self service mode. Frequently these customers have questions best answered by human ACD agents. With this invention the connection between the customer with the question and the agent with the answer is done quickly and efficiently with both parties sharing screens of common information. Also control is retained by the customer to make the call happen when they want it.

Abstract: Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnection controller. Intra-cluster links are formed between the local nodes, including the interconnection controller, within a cluster. Inter-cluster links are formed between interconnection controllers of different clusters. Intra-cluster packets may be serialized and encapsulated as inter-cluster packets for transmission on inter-cluster links, preferably with link-layer encapsulation. Each inter-cluster packet may include a sequence identifier and error information computed for that packet. Clock data may be embedded in symbols sent on each bit lane of the inter-cluster links. Copies of transmitted inter-cluster packets may be stored until an acknowledgement is received.

Abstract: A system and corresponding method use a PAUSE instruction as a low power hint in a single threaded or multithreaded environment using “processor slow mode.” One embodiment actually lowers the frequency of the processor clock. Another embodiment virtually lowers the frequency of the processor clock by gating M clock cycles out of every N clock cycles. When all threads have issued a PAUSE instruction, the processor enters slow mode and remains there for a while. After this while, the processor returns to normal mode. Alternatively, an event, such as an interrupt or an exception, can cause the processor to return to normal mode from slow mode.

Abstract: A method and system to provide platform-based optimization routines by firmware of a computer system. During a pre-boot phase of a computer system, the firmware identifies one or more hardware devices, such as a central processing unit (CPU) or chipset, of a computer system. The firmware determines an optimized routine library for the one or more hardware devices from a set of optimized routine libraries. The firmware advertises the optimized routine library corresponding to the one or more hardware devices to the computer system for use by an operating system or application. In one embodiment, the firmware of the computer system operates in accordance with the Extensible Firmware Interface (EFI) framework standard.

Abstract: A method and system for power management including local bounding of device group power consumption provides the responsiveness of local power control while meeting global system power consumption and power dissipation limits. At the system level, a global power bound is determined and divided among groups of devices in the system so that local bounds are determined that meet the global system bound. The local bounds are communicated to device controllers associated with each group of devices and the device controllers control the power management states of the associated devices in the group to meet the local bound. Thus, by action of all of the device controllers, the global bound is met. The controllers may be memory controllers and the devices memory modules, or the devices may be other devices within a processing system having associated local controllers.

Abstract: Methods and systems are provided for dynamically managing the power consumption of a digital system. These methods and systems broadly provide for varying the frequency and voltage of one or more clocks of a digital system upon request by an entity of the digital system. An entity may request that the frequency of a clock of the processor of the digital system be changed. After the frequency is changed, the voltage point of the voltage regulator of the digital system is automatically changed to the lowest voltage point required for the new frequency if there is a single clock on the processor. If the processor is comprised of multiple processing cores with associated clocks, the frequency is changed to the lowest voltage point required by all frequencies of all clocks.

Abstract: Embodiments of the present invention are described in an integrated circuit. The integrated circuit comprises circuit elements configured to be clocked via an oscillating signal, and a detector. The detector is configured to detect a state of the oscillating signal and provide a detection signal indicative of the state of the oscillating signal. The detector comprises a first delay line configured to provide a first delayed signal to logic that provides the detection signal.

Abstract: Methods, apparatus, systems, and articles of manufacture for maintaining virtual real time clocks (virtual RTCs) in a logically partitioned computer system are described. Changes made to a hardware real time clock (hardware RTC) while a partition manager is not running (or is not fully operational) are tracked. The cumulative effect of these changes on the hRTC value may be captured in a clock delta variable. For some embodiments, a service processor may be configured to track the changes to the hRTC while the partition manager is not running and generate the clock delta. Upon loading, the partition manager may utilize this captured clock delta to make adjustments to vRTCs, in an effort to preserve their integrity by compensating for the changes made to the hRTC while the partition manager was not running.

Abstract: Systems and methods are discussed to identify a recoverable state in a low power device. A low power device having an arbiter to grant system bus access to a plurality of bus masters is set to initiate a low power mode of operation. A low power controller within the low power device provides a request to the bus arbiter to initiate a low power mode. The bus arbiter stops granting bus requests to the bus masters and identifies when the system bus has processed all current bus accesses. When the system bus is idle, the bus arbiter returns a bus grant signal to the low power controller. Clocks associated with the bus masters are disabled to suspend the bus arbiters and allow less power to be consumed by the low power device.

Abstract: The present invention provides a method and a control apparatus (1) for sequentially controlling the spinning up of a number of IDE_HDDs (30) included in one computer or network server. The method and apparatus works by assigning different ID numbers to different pairs of IDE_HDDs and causing a delay between the start of spin up of each pair. The control apparatus includes a host (10), a plurality of controllers (20), a plurality of power switches (40) and a plurality of IDE_HDDs. When the control apparatus is booted up, each controller receives an ID number from the host and delays activating the power switches connecting a power supply (50) to the IDE_HDDs by a time proportional to the ID number. The present invention thereby avoids too high an instantaneous peak current during booting up and prevents the power supply from being burnt out.

Abstract: Disclosed is a system having a power input line. A power supply facility provides the system with a combined set of signals including a power signal and a status signal over the power input line. Additionally, disclosed is a system having at least two power input lines. Uninterruptible power supply facilities provide the system with combined sets of signals including a power signal and a status signal over the power input lines. Each combined set of signals includes a unique UPS identifier, which can be used to determine whether power sources for power input lines are unique.

Abstract: The specification may disclose a system and related method for control of a server system that may include determining the amount of power delivered in a system utilizing redundant power supplies based on a measurement of the voltage of load share signals between those power supplies, and then allowing additional servers installed in the server system to power-on only if the amount of power required for the combined servers does not exceed the maximum available power or exceed the power required for a certain type of redundant power supply operation.

Abstract: A computing system that incorporates an auxiliary processor to the main system processor. The auxiliary system utilizes a separate application runtime for processes and is capable of operating even when the primary system is in an off state. Methods for load-balancing are provided based on computing needs respective to power consumption requirements. Processes that are not computationally intensive are processed by a low-power, auxiliary processor. In addition, peripheral components accessible to the overall computing system are shared.

Abstract: Processing circuits that are associated with the operation of threads in an SMT processor can be configured to operate at different performance levels based on a number of threads currently operated by the SMT processor. For example, in some embodiments according to the invention, processing circuits, such as a floating point unit or a data cache, that are associated with the operation of a thread in the SMT processor can operate in one of a high power mode or a low power mode based on the number of threads currently operated by the SMT processor. Furthermore, as the number of threads operated by the SMT operator increases, the performance levels of the processing circuits can be decreased, thereby providing the architectural benefits of the SMT processor while allowing a reduction in the amount of power consumed by the processing circuits associated with the threads. Related computer program products and methods are also disclosed.

Abstract: A system and method for predicting whether a dynamic reconfiguration of a resource of a resource domain would be successful, prior to attempting the reconfiguration. A resource domain includes one or more computer resources (e.g., physical, logical and pseudo devices) and a graph management agent configured to maintain a graph representing the resources and dependencies between resources. Vertices of the graph represent resources; edges represent dependencies. A resource domain may also include a set of policies or constraints regarding resources and reconfigurations of resources. An illustrative constraint may specify that a particular resource (e.g., a multi-pathed logical device) must have a minimal number of paths (e.g., two). The graph agent identifies the effect the dynamic reconfiguration operation would have upon the resources and dependencies, and determines whether any constraints would be violated.