Abstract: A memory system that includes a plurality of memory devices includes: a controller for outputting a first clock signal, a second signal and a plurality of command/address input signals corresponding to the plurality of memory devices, respectively; and a register and delay circuit unit for outputting command/address output signals after receiving the command/address input signals front the controller and then correcting transmission delay due to transmission lines; wherein the plurality of memory devices receive the command/address output signals from the register and delay circuit unit via the transmission lines, respectively, and sample the command/address output signals using the first clock signal directly inputted from the controller. As a result, the memory system can simplify the layout of semiconductor device design and prevent the collision of clocks.

Abstract: Disclosed is a method, apparatus, and system in which a basic input/output BIOS is run and a non-volatile memory coupled to the BIOS is read. The BIOS determines if legacy partition address data is not present for a disk partition identified in the non-volatile memory, and if legacy partition address data is not present for the disk partition, the BIOS causes the execution of a Legacy OPROM. The execution of the Legacy OPROM causes legacy partition address data for the disk partition that does not have associated legacy partition address data to be obtained. The non-volatile memory as well as the disk drive is updated with the legacy partition address data.

Abstract: An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.

Abstract: An apparatus, program product and method utilize a nonvolatile solid state memory organized so as to store variable amounts of configuration data for a logically-partitioned computer in an efficient, compact and cost-effective manner. A nonvolatile solid state memory is partitioned into fixed size blocks that are linked together into chains for the purpose of storing variable amounts of configuration data for a plurality of logical entities, e.g., logical partitions, hardware devices, networks, and other resources. A chain of fixed size blocks is used to maintain configuration data for a given type of logical entity, with each block in a chain storing configuration data for a particular logical entity of the associated entity type. The fixed size blocks include full blocks and shared blocks, with full blocks storing data for a single logical entity, and shared blocks storing data for multiple logical entities of a common entity type.

Abstract: Disclosed is a clock distribution device and method in a compact PCI system based multi-processing system. A compact PCI based multi-processing system preferably includes processing signals upon mounting various circuit boards on multiple slots, even if the location of the system slot is varied, the skew of clocks transmitted to the other slots may be minimized. Accordingly, the system may be configured in a flexible manner because of such variability of the system slot's location. Further, the system may be efficiently repaired and maintained because it is possible to easily and quickly take measures in response to any failure occurring on the board mounted on the system slot.

Abstract: In an embodiment of the invention, a system includes a direct memory access (DMA) engine to move data on a real time basis and a communication front-end to transmit and receive the data. In another embodiment, the system may also include a medium access control (MAC) to control transmission and reception of the data and that may be partitioned or divided according to response times to carry out selected functions. Other embodiments of the invention are described and claimed.

Abstract: A detector detects information about a firmware system. The detector includes an interface that receives a generic instruction. The generic instruction may be a function call made through an EFI shell. The detector has a controller communicatively connected to the interface. The controller receives the generic instruction and gathers information about the firmware system. Gathering information about the firmware system permits platform-specific firmware system functions to be written to the firmware system. The controller gathers information about the firmware system by accessing a data-gathering function based on the generic instruction. The controller retrieves the information through the data-gathering function and transfers the information to the interface.

Abstract: An integrated circuit includes at least a first fuse and at least a first processor. Each fuse is in either a conductive state or a non-conductive state. The first processor is configured to operate at one of at least a first issue rate or a second issue rate responsive to the state of the first fuse. The first issue rate is lower than the second issue rate. In another embodiment, the first processor is configured to execute fewer instructions in a period of time responsive to a first state of the conductive state or the non-conductive state of the first fuse than the first processor is configured to execute in the period of time responsive to a second state of the first fuse. A method includes: (i) determining if an integrated circuit comprising at least one processor has a performance rating that exceeds a government-imposed export restriction; and (ii) in response to the performance rating exceeding the export restriction, blowing at least one fuse on the integrated circuit.

Abstract: A data transmission error reduction circuit is formed including a delay circuit, a detection circuit and a control circuit. In one embodiment, the delay circuit includes n delay element and multiplexor pairs, selectively employable to apply an aggregate amount of time delay to a data signal. The detection circuit includes circuit elements to detect a critical reference time distance between a reference point of a data signal and at least a selected edge of a clock signal being smaller than a desired threshold. The control circuit includes circuit elements to dynamically control the aggregate amount of time delay applied by the delay circuit based at least in part on the detection of the detection circuit. In one application, m units of the data transmission error reduction circuit are correspondingly employed to reduce data transmission errors on m high speed parallel data signals of a data interface.

Abstract: A panel device mounted on a computer case comprises an adjustment unit for adjusting CPU's operating frequency, a display module for showing system information, and a microprocessor which interconnects the adjustment unit and the display module with the computer system. The microprocessor can perform adjustment done by the adjustment unit and issue a service request signal to the computer. In response, the computer issues signals about system information to the microprocessor for being processed and showed on the display module.

Abstract: A computer system 10 with one or more processors 12 can be configured to operate in any one of a number of thermal environments. A setting system 14 sets operating parameters of the computer system such as processor operating voltage and frequency. A selecting system 16 selects values of operating parameters for use in setting by responding to an input of configuring data 20 to select a set of parameter values from a parameter value storage memory 18. The configuring data 20 may be input by the insertion of a smart card 58. Such configuring is useful in adapting computer systems during manufacture for compliance with desired specifications without hardware modification.

Abstract: A circuit for data transfer includes a first buffer operating at a first clock frequency, a plurality of second buffers operating at a second clock frequency, and a selector circuit which receives data at the first clock frequency, and supplies the data to a selected one of the first buffer and the second buffers.

Abstract: A distributed power management technique allows controlling power states of devices separated from a power management controller, such as a processor, by an interconnect. The power management controller inserts power state information into an interconnect transaction. An interconnect connected device then extracts the power state information and modifies the power state of the device responsive to the power state information. The power state information can be extracted by a processor that then controls the power state of another device responsive to the power state information.

Abstract: A semiconductor device includes a clock generation unit which generates a clock signal, a first module which asserts a clock-control request signal, and one or more second modules, each of which receives the clock signal and the clock-control request signal, and asserts a clock-control acknowledge signal after stopping an operation thereof upon completion of a currently performed operation in response to the assertion of the clock-control request signal, wherein the clock generation unit selectively changes the clock signal supplied to the one or more second modules in response to assertion of all clock-control acknowledge signals output from the one or more second modules.

Abstract: A data processing system (100) comprises a system bus (120), a plurality of devices (110, 150, 160, 170) coupled to the system bus (120), a bus monitor circuit (140), and a clock generator (130). The plurality of devices (110, 150, 160, 170) includes at least one bus master (110, 150) which is capable of performing accesses on the system bus (120). The bus monitor circuit (140) is coupled to the at least one bus master (110, 150), and has an output for providing a bus idle signal to indicate that no bus master is attempting to perform an access on the system bus (120). The clock generator (130) has an output coupled to at least one of the plurality of devices (110, 150, 160, 170) and provides a bus clock signal having a first frequency when the bus idle signal is inactive and having a second frequency lower than the first frequency when the bus idle signal is active.

Abstract: The present invention facilitates the operational management and usability of a portable computing device by providing an apparatus, method and program product to allow a user to select the operational and power state of a device operably connected with a computer and the power state of the computer prior to removing the computer from an apparatus such as a docking station.

Abstract: A method of using a dynamic computing environment to facilitate a sales preparation of a first software is provided. The method comprises configuring the dynamic computing environment for a first hardware, a first software environment and a first network configuration, preparing for sales of the first software using the first hardware, the first software environment, and the first network configuration of the dynamic computing environment, configuring the dynamic computing environment for a second hardware, a second software environment, and a second network configuration; and preparing for sales of the first software using the second hardware, the second software environment, and the second network configuration of the dynamic computing environment. A method of using dynamic computing environments to facilitate a sales demonstration by a sales team and an evaluation by a customer is also provided.

Abstract: A microcontroller includes a clock circuit with a register storing clock frequency information corresponding to a low speed or normal mode respectively operated by a low frequency or normal clock, which outputs a first signal according to a value set in the register when the low speed mode is designated during operation in the normal mode, a DRAM holding data, in the low speed mode, by operation in a self-refresh mode, and outputting a confirmation signal indicating switching to that mode, a DRAM circuit switching the DRAM to that mode based on the first signal, a ROM operated in the low speed mode, a remap circuit controlling an address circuit based on the confirmation signal, and outputting a second signal for switching a program execution address from the DRAM to an address of the ROM to control an address space in which a program is executed, the address circuit switching the address space based on the second signal.

Abstract: A microcomputer and method for same can contain a nonvolatile memory module and store information regarding various system models in the memory module to support the various system models by one keyboard BIOS. Functions preset in the microcomputer, which includes a keyboard controller are not removed even though system voltages are removed so the preset functions are maintained. Preferably, the microcomputer includes a nonvolatile memory module for storing desired, prestored information even when system voltages are removed, and a keyboard controller module for performing control operations of a keyboard with a keyboard basic input/output system (BIOS). The desired information can include function information set by a user, current status information, and design selection information for designing the keyboard BIOS appropriately to an applied system.

Abstract: A method and apparatus including a first circuit configured to receive multiple instructions including a first instruction having a first execution time, and to generate a first signal having a state dependent on the first execution time; a second circuit configured to receive the first signal and to generate a clock signal including a clock cycle having a period dependent on the state of the first signal; and a third circuit configured to receive the clock signal and execute a portion of the first instruction during the clock cycle, the first execution time corresponding to the portion of the first instruction.

Abstract: A method and apparatus for resonant frequency testing of free standing turbine blades made of a material, such as titanium, that is not responsive to a magnetic field is disclosed. A lightweight shim 12 made of a magnetically responsive material such as steel, weighing on the order of 0.5 grams, is attached to the convex side of the blade 10. The shim 12 is excited by an oscillating magnetic field and moves the blade 10 accordingly. The maximum amplitude of blade 10 movement is recorded and used to determine the resonant frequency as the excitation frequency of the magnetic field is swept through a frequency window range. The low weight of the shim 12 does not materially change the resonant frequencies of the blade 10.