Abstract: A computer system includes a voltage regulator that supplies power to a component. The component may provide a signal indicating an amount of current the component consumes under a high utilization operating condition. The voltage regulator may then determine the slope of a load line using this signal.

Abstract: Techniques are disclosed for resetting agents in a computer system without requiring the computer system, or partitions thereof, to be reset. In one embodiment, each agent in the system is associated with a corresponding partition. A reset signal directed to an agent is redirected to a reset type selector which determines whether the partition associated with the agent is in a run state (an “unsafe run state”) in which resetting the agent will cause the partition to crash. If the partition is in an unsafe run state, a soft reset is performed on the agent. Otherwise, a hard reset is performed on the agent. If performing a soft reset does not solve the problem that was the impetus for the reset signal, the partition may be brought into a safe run state before performing a hard reset on it.

Abstract: Prior to the loading of a main program, the rotation speed of a disk provided in a hard disk drive is increased to a common rotation speed adapting to all types of hard disk drive. At the common rotation speed and a common recording density, a main program is read from a system area in the disk where the main program is recorded. The main program is written to a RAM provided in a hard disk controller. After control processing of the hard disk drive is handed over to the main program, the rotation speed of the disk is increased to a proper rotation speed for a device. This allows main programs to be loaded in a common way from disks provided in respective hard disk drives independent of the type thereof.

Abstract: In one embodiment of the invention, a performance information associated with a processor is read. A processor performance table that corresponds to the performance information is located. The performance table includes a plurality of performance parameters to control performance of the processor. A performance state (PS) structure is updated using one of the processor performance table and a default table.

Abstract: A method, apparatus, and computer instructions for determining validity of and updating a microcode image. Responsive to initiation of an update process, a first validity indicator is checked to determine whether a first microcode image in the memory is valid. In response to the first microcode image being valid, a second validity indicator is set indies, to indicate that a second microcode image is invalid, and the update process is allowed to update the second microcode image to form an updated microcode image. A determination is made as to whether the updated microcode image is valid. The second validity indicator is set to indicate that the updated microcode is valid if the updated image is valid. The second validity indicator is checked during booting of a data processing system. If the second validity indicator is valid, the updated microcode will be loaded.

Abstract: A data processing system includes first, second, and third agents connected to a shared bus. The third agent is able to receive information via the shared bus from the first agent or from the second agent. The third agent includes a skew compensation circuit to determine signal skew in signal received via the shared bus and to compensate for the skew by adding delay into selected signals of the bus. The skew compensation circuit determines whether the first agent or the second agent is the sender of information received by the third agent via the shared bus. The skew compensation circuit alters the skew compensation based on the identity of the sender such that the delay into the bus signals is specific to the corresponding sender.

Abstract: A method and apparatus for handling power consumption of a bus-controlled component such that the power requirements of the bus-controlled component are met without drawing excessive power from the computer bus. The apparatus of the present invention includes two embodiment of a bus power handling device that enables power to be obtained directly from a power supply and from a bus slot. In a first embodiment, the bus power handling device fits between the bus slot and the bus-controlled component and enable the component to obtain power directly from a power supply and from the bus slot. In a second embodiment, the bus power handling device is located on the bus-controlled component and allows connection to the power supply and the bus slot. The method of the present invention includes a technique to draw additional power required for the bus-controlled component directly from a power supply.

Abstract: A system and method for reducing the power consumption in a floating point unit of a processor executing an iterative loop of a program by inhibiting floating point register file writes of interim values of the loop from the floating point multiply adder (FPMADD) unit. A plurality of pipeline registers is resident on the processor and holds a portion of an unrolled loop, and once the end of the loop is detected, the last value produced from the loop in the FPMADD unit is written to the floating point registers.

Abstract: In one embodiment of the invention, a processor state of a processor is determined upon expiration of a system management interrupt (SMI) timer. The processor state is one of an operational state and a low power state. The SMI timer is loaded with a timer value based on the processor state. The timer value is one of a first value and a second value. The processor is transitioned to one of the operational state and the low power state according to the processor state.

Abstract: A low-speed DLL facilitates a deskewed interface between a high-speed RX data demultiplexer circuit directly to an Application Specific Integrated Circuit (ASIC) with which it is integrated by locking a 156 MHz ASIC clock to a 156 MHz reference derived from a high speed 2.5 GHz clock. The DLL employs a digital interpolator to generate 32 phases of the 156 MHz clock. The digital interpolator supplies the phases using a double clocked shift register with recirculating feedback. The shift register is double clocked using the 2.5 GHz clock. The register outputs are tapped and fed to a 32:1 multiplexer having a phase select input that is controlled by the phase difference signal generated by the DLL. The phase difference control signal is converted to a digital representation of its magnitude by which the requisite number of phase shift increments may be selected.

Abstract: A data clock for use in data communication between the connected processors and a system clock for use in data processing within the own processor are made independent and asynchronous in clock rate and adjustment between the two clocks is performed by an enable creating unit. According to the data processing enable signal created by the two clocks, a timing of the data processing is controlled and the data is processed at a high speed by the system clock.

Abstract: A system and method for configuring devices during pre-boot in a computer system which may have both legacy and EFI compatible option-ROMs. EFI versions of the Option-ROMs export a callable interface that can be invoked to execute the configuration utility. A hardware independent piece of software lists all the hardware devices in a single menu and allows the user to invoke the configuration utility for the appropriate hardware device(s).

Abstract: A system architecture and method are provided for synchronizing the slave clock of one or more resources with the master clock of a controller in a document processing system. The method includes: a) saving a value of the master clock (615); b) generating a discrete clock synchronization interrupt signal and distributing the interrupt signal to the resource(s) via the control bus (625); c) receiving the interrupt signal at each resource (630) and saving a value of the slave clock (640); d) sending a message to the controller via a network to request the value saved for the master clock (645); e) sending the value to the resource (660); f) receiving the value (665); and g) subtracting the value saved for the slave clock from the value saved for the master clock to determine an error value between the clocks (690) and using the error value in an adjustment algorithm to synchronize the slave clock with the master clock (695).

Abstract: A power supply circuit for a digital processing system. A first stage of the power supply circuit is used to generate power for a first component of the digital processing system and to drive a second stage of the power supply circuit. The second stage of the power supply circuit supports a second component of the digital processing system. The first and second stages of the power supply circuit are electrically connected to each other.

Abstract: A method of rapid booting and switching between applications of a computer system. A software solution is used to implement hot key switching and hot key functions in a computer system to enable rapid booting and switching between applications.

Abstract: A source synchronous bus system is provided with a bus; a first device connected to the bus, having a driver to drive data and strobe signals, via the bus; and a second device connected to the bus, having a receiver to receive data and the strobe signals from the bus, and to select one of rising and falling edges of the strobe signals to latch a corresponding one of rising and falling edges of the data received from the bus, for subsequent data processing functions in order to compensate for systematic differences between rising and falling edges of the data received, via the bus.

Abstract: An oscillation circuit generates a reference clock signal for a clock signal supplied to each section of a data transfer control device. In a clock output control circuit, a clock command is decoded by a clock command decoder and oscillation of the oscillation circuit is controlled. The data transfer control device including a clock control circuit transfers data as a host or a peripheral in a state being set to either a self-powered first device or a second device which can operate by using a power supply on a bus. The oscillation operation of the oscillation circuit is suspended in an idle state of the second device.

Abstract: A managing apparatus has a RAM for storing power saving mode shift time and notifies output apparatuses of the stored power saving mode shift time via a network. Each output apparatus is shifted to a power saving mode when measured time by a built-in timer reaches the notified power saving mode shift time.

Abstract: Methods and computer systems provide for the selection of a DSDT that accurately describes a current configuration of the computer system. Because the system configuration can change over time, such as due to hardware malfunctions or the addition or removal of hardware requiring a BIOS interface to software, multiple DSDTs are available for selection so that for each computer system configuration, an appropriate DSDT is available. Upon boot-up, the hardware of the computer system is analyzed to determine the set of available North Bridge chipset devices. An appropriate DSDT is then selected from a set of multiple DSDTs for the current computer system configuration.

Abstract: A selective quick boot system and method. The selective quick boot system includes a control module and a processing module with an event table. The control module receives a quick signal, provides power enabling the processing module, an event code corresponding to the quick signal is then transferred to the processing module. The processing module compares the received event code to the event table to locate a corresponding item, and drives the device recorded as the corresponding item and executes the associated application also recorded in the event table.