Abstract: A system and method for processing a block Low Density Parity Check (LDPC) code are provided. The system includes, a decoding apparatus for decoding a block LDPC code using a parity check matrix, the parity check matrix including an information part and a parity part, the parity part including a first section (B) including a plurality of first permutation matrices, a second section (D) including a second permutation matrix, a third section (T) including a plurality of identity matrices (I) arranged diagonally within the third section and a plurality of third permutation matrices arranged below the plurality of identity matrices, and a fourth section (E) including a fourth permutation matrix.

Abstract: Encoding/decoding memory devices and methods thereof may be provided. A memory device according to example embodiments may include a memory cell array and a processor including at least one of a decoder and an encoder. The processor may be configured to adjust a redundant information rate of each channel, where each of the channels is a path of the memory cell array from which data is at least one of stored and read. The redundant information rate may be adjusted by generating at least one codeword based on information from a previous codeword. Therefore, example embodiments may reduce an error rate when data is read from and written to the memory device.

Abstract: Apparatuses of wireless subscribers that manage storage of HARQ packets are disclosed. One embodiment of a wireless subscriber includes receiver circuitry for wirelessly receiving HARQ packets. CRC processing circuitry checks an error status of the received HARQ packets. A HARQ memory controller divides the HARQ packets into HARQ sub-packets for storage in HARQ memory. The HARQ memory controller records storage locations and a storage order of each of the HARQ sub-packets.

Abstract: In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block.

Abstract: Briefly, techniques to provide varying levels of enhanced forward error correction without modifying a line rate of a frame.

Abstract: This invention is a memory system with parity generation which selectively forms and stores parity bits of corresponding plural data sources. The parity generation and storage depends upon the state of a global suspend bit and a global enable bit, and parity detection/correction corresponding to each data source.

Abstract: A parallel residue arithmetic operation unit is provided to reduce processing delay, and to make an additional multiplier or a residue arithmetic circuit unnecessary, so that a circuit can become small in size. In the parallel residue arithmetic operation unit, a parallel CRC calculation circuit includes input terminals to which input data are divided into a plurality of sub-blocks and the sub-blocks are input in parallel, an initial value generating unit for generating a part CRC corresponding to the forefront of each sub-block as an initial value, a part CRC generating unit for receiving the part CRC corresponding to the forefront of each sub-block as the initial value and sequentially generating a residue part CRC in accordance with a recurrent equation, AND units for calculating logical multiplications of part CRC values, and a cumulative adding unit for cumulatively adding values output from the AND units.

Abstract: A cache memory built in a processor comprising a plurality of independent memory blocks, pass/fail information memory unit memorizing a presence/absence of a failure occurring in each of the memory blocks, and a screening control function substituting a sound memory block for a failed memory block based on a memory content in the pass/fail information memory unit.

Abstract: Error detection and error location determination circuitry is provided for detecting and locating soft errors in random-access-memory arrays on programmable integrated circuits. The random-access-memory arrays contain rows and columns of random-access-memory cells. Some of the cells are loaded with configuration data and produce static output signals that are used to program associated regions of programmable logic. Cyclic redundancy check error correction check bits are computed for each column of an array. The cyclic redundancy check error correction check bits are stored in corresponding columns of cells in the array. During normal operation of an integrated circuit in a system, the cells are subject to soft errors caused by background radiation strikes. The error detection and error location determination circuitry uses parallel processing to continuously monitor the data to identify the row and column location of each error.

Abstract: A technique of determining a message residue includes accessing a message and simultaneously determining a set of modular remainders with respect to a polynomial for different respective segments of the message. The technique also includes determining a modular remainder with respect to the polynomial for the message based on the set of modular remainders and a set of constants determined prior to accessing the message. The modular remainder with respect to the polynomial for the message is stored in a memory.

Abstract: A test system includes a supervisor unit coupled to a control interface; the control interface coupled to first and second test modules, each test module comprising a first logic module to test macro blocking errors; a second logic module to perform optical character recognition; a third logic module to perform signal to noise ratio measurement; and a fourth logic module to perform random noise measurement; each test module coupled to a device under test, the four logic modules applied to test a menu-driven video decoding device.

Abstract: Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter includes an input padding module configured to provide padded bits having padding bits added to payload bits for one or more control channels, and a scrambling module configured to apply a masking sequence to one or more of the padded bits to generate scrambled bits. Additionally, the transmitter also includes an encoding module configured to perform forward error correction encoding and rate matching on the scrambled bits to obtain a required number of control channel output bits, and a transmit module configured to transmit the control channel output bits for one or more control channels.

Abstract: The invention relates to a method of encoding user data into codevectors and to a corresponding method of decoding codevectors into user data.

Abstract: A flexible and relatively hardware efficient LDPC decoder is described. The decoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process. Each command of a relatively simple control code used to describe the code structure can be stored and executed multiple times to complete the decoding of a codeword. Different codeword lengths are supported using the same set of control code instructions but with the code being implemented a different number of times depending on the codeword length. The decoder can switch between decoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor that is indicative of codeword length and is used to control the decoding process. When decoding codewords shorter than the maximum supported codeword length some block storage locations may go unused.

Abstract: An apparatus and method are disclosed to receive information and to generate, store, and read, a plurality of error correction coded data sets using that information. Applicants' storage controller receives information and generates (N) sets of error correction coded data, wherein (N) is greater than or equal to 2. The method writes, for each value of (i), the (i)th set of error correction coded data to the (i)th data storage medium, wherein (i) is greater than or equal to 1 and less than or equal to (N). If Applicants' storage controller receives a request to read the information, then Applicants' method reads each of the (N) error correction coded data sets, generates the information using the (N) error correction coded data sets, and returns the information to the requestor.

Abstract: The present invention provides systems and methods for implementing cyclic redundancy checks to improve link initialization processing and to exchange system error information. In one aspect, a cyclic redundancy check (CRC) checker is provided that includes a unique pattern detector, a CRC generator, a CRC initializer and a CRC verifier. The CRC checker prepopulates the CRC generator for a unique pattern. Upon receipt of the unique pattern within a data stream received over a digital transmission link, the CRC checker proceeds to check CRCs without the need to queue and store data. In another aspect, a CRC generator system is provided that intentionally corrupts CRC values to transmit system error information. The CRC generator system includes a CRC generator, a CRC corrupter, an error detector and an error value generator. In one example, the digital transmission link is an MDDI link.

Abstract: Error detection and error location determination circuitry is provided for detecting and locating soft errors in random-access-memory arrays on programmable integrated circuits. The random-access-memory arrays contain rows and columns of random-access-memory cells. Some of the cells are loaded with configuration data and produce static output signals that are used to program associated regions of programmable logic. Cyclic redundancy check error correction check bits are computed for each column of an array. The cyclic redundancy check error correction check bits are stored in corresponding columns of cells in the array. During normal operation of an integrated circuit in a system, the cells are subject to soft errors caused by background radiation strikes. The error detection and error location determination circuitry uses parallel processing to continuously monitor the data to identify the row and column location of each error.

Abstract: Various embodiments of the present invention provide methods and apparatuses for multi-level layer decoding of non-binary LDPC codes. For example, an apparatus is disclosed for layer decoding of multi-level low density parity check encoded data. The apparatus includes a low density parity check decoder operable to perform layered decoding of a plurality of circulant submatrices from an H matrix. The apparatus also includes a parity check calculator connected to the low density parity check decoder, operable to detect whether a stopping criterion has been met in the low density parity check decoder. The low density parity check decoder is also operable to end a decoding operation at less than a maximum number of iterations when the stopping criterion is met.

Abstract: An error locator polynomial is incrementally generated by flipping a bit pattern Yi at a symbol Xi an initial dataword to obtain a first test error pattern. A bit pattern Yj at a symbol Xj within the first test error pattern is flipped to obtain a second test error pattern, wherein i?j.

Abstract: A system (e.g., Fiber Channel Error Detecting Code (FC-EDC)) that maps the “standard” Hamming codes onto the bits of a 33-bit control block is provided. The system employs a “rotation” of the check positions in a two-dimensional parity-check matrix for the FC-EDC. The specification discloses a computer-implemented program to test further modifications and permutations of the “standard” distance-4 parity-check matrix to yield an FC-EDC with enhanced error-detecting properties, designed to detect the most likely errors in the known physical environment. By using a parity-check matrix with the “rotation” property, certain error-detecting properties of the parity-check matrix are ensured, and the computation time for searching for a matrix with enhanced error-detecting properties becomes much shorter.