Abstract: Approaches for decoding data read from memory cells of a nonvolatile, solid state memory involve attempting to decode hard data using a hard decoding process prior to a time that soft data is available to the decoder. The hard data includes information about the digital symbols stored in the memory cells without data confidence information. The soft data includes information about the digital symbols stored in the memory cells and data confidence information. In response to the hard decoding process failing to achieve convergence, after the soft data becomes available to the decoder, the soft data is decoded using a soft decoding process. The decoder generates an output of the decoded data after the hard decoding process or the soft decoding process achieves convergence.

Abstract: A method includes encoding data bits into codewords according to a first error correction encoding scheme. The method includes storing the codewords into a memory and generating a combined codeword by encoding, at the memory, the codewords according to a second error correction encoding scheme to generate parity bits of the combined codeword. The method includes, after storing the codewords into the memory, storing the parity bits of the combined codeword into the memory.

Abstract: Techniques are presented for dealing with errors that arise from cluster fails, where a number of memory cells in the same area fail. An ECC code word can tolerate a given total amount of error while still being able to still be decoded, so that if error due to clusters can be identified and removed or lessened, it may be possible to still decode the word not otherwise decodable. After identifying possible error bit cluster locations, one or more bits in the cluster locations are flipped to see if the data content of the code word can be extracted. For embodiments using LDPC ECC code, uncertainty can be added for the bits of a suspected cluster location. To reduce the effects of cluster failures, code words can be interleaved within a page and the difference code words can have differing levels of ECC capability.

Abstract: Apparatuses and methods are provided for generating a plurality of redundancy versions using various rate matching algorithms. In some embodiments, a rate matcher is provided that allocates systematic and parity bits to the redundancy versions in a manner that allows all of these bits to be transmitted in at least one redundancy version. In some embodiments, the rate matcher uses a first puncturing algorithm to generate both a first redundancy version and a third redundancy version, but allocates a different proportion of the systematic bits to these redundancy versions. In these embodiments, the second redundancy version may include only bits that were not transmitted in the first redundancy version.

Abstract: A method and device for multiview distributed video coding with adaptive syndrome bit rate control are disclosed. In one embodiment, multiple groups, including video frames coming from associated digital cameras, are formed. Further, video frames coming from a predetermined number of the digital cameras are declared as key video frames. Furthermore, video frames coming from remaining digital cameras are declared as non-key video frames. In addition, the key video frames are encoded to obtain encoded bits. Moreover, the non-key video frames are encoded to obtain syndrome bits. Also, the encoded key video frames are decoded, to obtain decoded bits and the encoded non-key video frames are decoded, to obtain decoded bits and CRC bits. Further, an optimal number of syndrome bits in each non-key video frame are determined. Furthermore, the encoded bits and determined optimal number of syndrome bits are sent to multiple receivers.

Abstract: A method is provided of encoding data within a RAID stripe, the RAID stripe being spread across k data disks and r redundancy disks of a RAID group, r?3, the RAID group having k+r disks, the k data disks and the r redundancy disks within the RAID stripe being distinct, such that, upon failure of any r disks of the k+r disks of the RAID group, the data can be fully recovered using the Forney algorithm. The method includes (a) partitioning the data into k data symbols, (b) storing each of the k data symbols to a respective data disk of the k data disks, (c) generating r Reed-Solomon redundancy symbols by applying the Forney algorithm to the k data symbols, and (d) storing each of the r Reed-Solomon redundancy symbols generated by the Forney algorithm to a respective redundancy disk of the r redundancy disks.

Abstract: Integrated circuits with memory error detection and correction (EDC) circuitry are provided. The EDC circuitry may include first and second data registers and a comparator. The first data register may store data read from a selected frame. The second data register may be loaded with a predetermined bit stream. If a soft error is detected, correct bits generated using a logic function associated with the predetermined bit stream may be written back to the selected frame. In another suitable arrangement, the EDC circuitry may include first and second registers, a mask register, and a comparator. The first data register may store data read from a selected frame. The second data register may be loaded with desired data. The mask register may be loaded with mask bits. If a soft error is detected, the correct bits may be written back to the selected frame if the corresponding mask bits are high.

Abstract: According to one embodiment, a memory device comprises a writing device that writes data bits, check bits for error corrections, and overhead bit(s) into a memory, each bit of the overhead bit(s) corresponding to each group of bit group(s) including at least one bit of the data bits and/or the check bits, each bit of the overhead bit(s) indicating whether the corresponding bit group has been inverted, a reading unit that reads the data bits, the check bits, and the overhead bit(s) from the memory, a correcting unit that corrects an error in the data bits and overhead bit(s) read from the memory, based on the check bits, and an inverting unit that inverts the data bits contained in the bit group corresponding to the overhead bit and outputs the inverted data bits as data read from the memory when the error-corrected overhead bit indicates that inversion has been performed.

Abstract: Methods and apparatus are described for reducing memory storage cells in a turbo decoder by storing only half the state metrics generated during a scan process. States associated with each bit transmission may be divided into couples and only one state from every state couple may be stored. In one example embodiment, only the state metric for a losing state of every state couple is saved, along with a single bit, e.g., 1 or 0, indicating whether the upper state or lower state of the state couple was the winner. The winning state may be reconstituted at a later stage. In this manner, for a code rate 1/3 and constraint length 3 turbo code, instead of storing 8*10=80 bits of state metrics for each systematic bit, only (4*10)+(4*1)=44 bits of scan state metrics data need be stored, a savings of nearly 50% regardless of the transistor technology used.

Abstract: The present technology relates to a data-processing device and a data-processing method, which are capable of improving tolerance for an error of data. When an LDPC code having a code length of 16200 bits is mapped to 16 signal points, a demultiplexer performs exchanging such that when a (#i+1)-th bit from a most significant bit of code bits of 4×2 bits and a (#i+1)-th bit from a most significant bit of symbol bits of 4×2 bits of 2 consecutive symbols are represented by a bit b#i and a bit y#i, respectively, for LDPC codes having coding rates of 1/5, 4/15, and 1/3, b0 is allocated to y4, b1 is allocated to y3, b2 is allocated to y2, b3 is allocated to y1, b4 is allocated to y6, b5 is allocated to y5, b6 is allocated to y7, and b7 is allocated to y0. For example, the present invention can be applied to a transmission system that transmits an LDPC code or the like.

Abstract: A memory read-channel is provided with selective transmission of error correction data. The disclosed read-channel improves throughput and reduces power consumption when error correction codes are unnecessary. The data read from a memory device comprises user data, error detection data and error correction data. In one embodiment, the error detection data is evaluated to determine if there is a data error; and the error correction data is transmitted only if a data error is detected. In another variation, the error detection data is evaluated during data transmission to determine if there is a data error and the transmission is suspended if a data error is detected. Typically, the error detection data comprises a cyclic redundancy check and the error correction data comprises parity check data.

Abstract: A data storage device may comprise a flash controller and an array of flash memory devices coupled to the flash controller. The array may comprise a plurality of S-Pages that may each comprise a plurality of F-Pages. In turn, each of the plurality of F-Pages may be configured to store a variable amount of data and a variable amount of error correction code. The flash controller may be configured to generate an error correction code across each F-Page of an S-Page and to store the generated error correction code within one or more F-Pages having the largest amount of data.

Abstract: Embodiments of the invention relate to erasure correcting codes for storage arrays. An aspect of the invention includes receiving a read stripe from a plurality of storage devices. The read stripe includes a block of pages arranged in rows and columns, with each column corresponding to one of the storage devices. The pages include data pages and parity pages, with the number of parity pages at least one more than the number of rows and not a multiple of the number of rows. The method further includes reconstructing at least one erased page in response to determining that the read stripe includes the at least one erased page and that the number of erased pages is less than or equal to the number of parity pages. The reconstructing is responsive to a multiple erasure correcting code and to the block of pages. The reconstructing results in a recovered read stripe.

Abstract: Methods of operating nonvolatile memory devices may include identifying one or more multi-bit nonvolatile memory cells in a nonvolatile memory device that have undergone unintentional programming from an erased state to an at least partially programmed state. Errors generated during an operation to program a first plurality of multi-bit nonvolatile memory cells may be detected by performing a plurality of reading operations to generate error detection data and then decoding the error detection data to identify specific cells having errors. A programmed first plurality of multi-bit nonvolatile memory cells and a force-bit data vector, which was modified during the program operation, may be read to support error detection. This data, along with data read from a page buffer associated with the first plurality of multi-bit nonvolatile memory cells, may then be decoded to identify which of the first plurality of multi-bit nonvolatile memory cells are unintentionally programmed cells.

Abstract: Embodiments of the present disclosure describe device, methods, computer-readable media and system configurations for decoding codewords using a side channel. In various embodiments, a memory controller may be configured to determine that m of n die of non-volatile memory (“NVM”) have failed iterative decoding. In various embodiments, the memory controller may be further configured to generate a side channel from n-m non-failed die and the m failed die other than a first failed die. In various embodiments, the memory controller may be further configured to reconstruct, using iterative decoding, a codeword stored on the first failed die of the m failed die based on the generated side channel and on soft input to an attempt to iteratively decode data stored on the first failed die. In various embodiments, the iterative decoding may include low-density parity-check decoding. Other embodiments may be described and/or claimed.

Abstract: According to one embodiment, a method for error correction in a memory module having ranks is provided where each rank has memory devices. The method includes determining a first mark condition for a first rank of the memory module, the first mark condition based on one or more uncorrectable error occurring in a first memory device in the first rank, placing a first mark in the first memory device, determining a second mark condition for the first rank, the second mark condition based on one or more uncorrectable error occurring in a second memory device in the first rank, placing a second mark in a third memory device in a second rank of the memory module and configuring the first memory device to respond to commands directed to the second rank, wherein configuring the first memory device is based on placing of the first mark and the second mark.

Abstract: Embodiments herein provide data recovery techniques and configurations for solid state memory devices. For example, a method includes identifying a hard error associated with a cell of a solid state memory device, providing a location of the cell having the identified hard error to a decoder to recover data originally programmed to the cell, and recovering the data originally programmed to the cell using the decoder. Other embodiments may be described and/or claimed.

Abstract: Disclosed is a solid state drive tester which divides the functions of generating and comparing test pattern data and Frame Information Structure (FIS) data with each other into each other to implement the functions as separate logics, so that entire test time is decreased by reducing load of a processor. The solid state drive tester includes a host terminal for receiving a test condition for testing a storage from a user, and a test control unit creating a test pattern corresponding to the test condition, and adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, wherein the test control unit is divided into a control module for controlling the test of the storage and a test execution module for practically executing the test in hardware to test a plurality of storages in real time.

Abstract: Embodiments provide a method comprising estimating a first set of log-likelihood ratio (LLR) values for a plurality of memory cells of a memory; based on the first set of LLR values, performing a first error correcting code (ECC) decoding operation; in response to determining a failure of the first ECC decoding operation, generating, by adjusting the first set of LLR values, a second set of LLR values for the plurality of memory cells; and based on the second set of LLR values, performing a second ECC decoding operation.

Abstract: Aspects of the invention relate to generating scan chain configurations for test-per-clock based on circuit topology. With various implementations of the invention, weight vectors between scan chains in a circuit are first determined. Based on the weight vectors, a scan chain configuration is generated by assigning some scan chains in the scan chains to a stimuli group and some other scan chains in the scan chains to a compacting group. Here, the stimuli group comprises scan chains to operate in a shifting-launching mode, and the compacting group comprises scan chains to operate in a capturing-compacting-shifting mode.