Abstract: The integrated circuit executes software programs. The electronic components of the integrated circuit and/or the electrical connections between them can be selectively broken and/or created. The wiring of the electronic components and/or their function and/or their mode of operation are thereby at least partly individually configured. The connections are thereby configured dynamically and in parallel during the operation of the integrated circuit.

Abstract: A RISC processor using a fixed length standard instruction word (32-bit) consisting of a fixed-length (6-bit) operation code and two register fields, uses one of the register fields to give certain operation codes multiple meanings. For most operations, the register codes refer to general purpose registers as such. However, for certain operations, including move and add, register codes 30 and 31 in the source register code field of the instruction word indicate that the next instruction word contains immediate data for that operation instead of the operand being located in the specified register itself. Further, for load, store and jump operations, the source register codes 30 and 31 in the source register code field indicates that those registers are to be used as base or index registers for indexed addressing, with an offset in the following instruction word added to the general purpose register 30 or 31 contents to form the address.

Abstract: A game system comprises a first storing device storing data for identifying strength and weakness of characters belonging to a player and an opponent; a first display control device for displaying a first game picture which expresses a state of a competitive game in which the player and the opponent compete by using the characters; an outcome determining device for determining an outcome of the competitive game based on the data stored in the first storing device; a second storing device storing data for identifying, with respect to a plurality of areas defined by dividing a predetermined field into a matrix, that each of the areas belongs to a territory of the player or the opponent; a second display control device for displaying a second game picture, on which the field is expressed in such a manner that the territory belonging to the player can be differentiated from the territory belonging to the opponent, based on the data stored in the second storing device; and a data updating device for changing the d

Abstract: A method used to test the correctness of image data transited between the system memory and display memory is described as follows. First, a image data A is stored in a location B of the system memory. Then, the data of image A and a location C of display memory are stored into a Bitblt temporary storage means. The Bitblt engine is used to transit the data of image A stored in the location B of system memory to the location C of display memory. Then, the data of location C, location D of display memory, and image A are input into the Bitblt temporary storage means. The Bitblt engine is used to transit the data of image A from the location C to the location D of display memory. The data of image A and location E are input into the Bitblt temporary storage means. The Bitblt engine is used to transit the data of image A from the location D into the location E of the system memory.

Abstract: The present invention relates to a method, apparatus and system for managing virtual memory, in which a co-processor (224) is adapted to use virtual memory with a host processor (202). A host memory (203) is coupled to the host processor (202) to implement the virtual memory. The co-processor (224) includes a virtual-physical memory mapping device (915) for interrogating a virtual memory table and for mapping one or more virtual memory addresses (880) requested by the co-processor (224) into corresponding physical addresses (873) in the host memory (203). The virtual memory table is stored in two or more non-contiguously addressable regions of the host memory (203), and is preferably a page table. The memory mapping device (915) further includes a multiple-entry translation lookaside buffer (889) for caching virtual-to-physical address mappings (872), where entries in the buffer (889) are replaced on a least recently used replacement basis.

Abstract: A system is provided for handling an error by identifying an activity that generated the error. The system determines whether the activity has an associated user-defined error handling process. If the activity has an associated user-defined error handling process, then the system executes the associated user-defined error handling process. If the activity does not have an associated user-defined error handling process, then the system executes a default error handling process. A particular activity my have multiple associated user-defined error handling processes. The system selects among the multiple user-defined error handling processes using one or more error handling parameters. The system includes an activity execution module configured to execute process definitions and identify errors that occur when executing process definitions.

Abstract: A liquid crystal driving integrated circuit (101) mounted directly on a liquid crystal substrate, wherein the integrated circuit (101) comprises a plurality of power supply terminal arrays, each of which include a high voltage power input terminal (102), (112), a low voltage power input terminal (103), (113), and an intermediate voltage power input terminal (130), (131) and a plurality of signal input terminal arrays (104)-(108), (114)-(118). A substantially rectangular integrated circuit chip (101) containing the integrated circuit is divided into two halves along a line (123) intersecting, at right angles, the longer sides of the chip. A first power supply terminal array (102), (103), (130) and a first signal input terminal array (104)-(108) are provided on one half of the divided chip, and a second power supply terminal array (112), (113), (130) and a second signal input terminal array (114)-(118) are provided on the other half thereof.

Abstract: A computer analyzes a printing instruction received from the user, and recognizes situations, e.g., properties and status, of available printers. When analysis of the printing instruction results in that a process instructed from the user is, for example, to print a colored document and an apparatus instructed to execute the process is a monochromatic printer, and recognition of the situations results in that an available color printer exists, the computer determines that the instructed printing process of the colored document should be instructed to not the monochromatic printer having been instructed, but the color printer, and then issues to the user an inquiry as to whether to print the document using the color printer.

Abstract: A invention relates to a method for representing variable information on a display device, in particular in a motor vehicle, having a first, dot matrix display having a liquid crystal cell, and having a second display having a liquid crystal cell, the second display being arranged optically in series with the first display, and the liquid crystal cell of the first display being driven using a multiplex method.

Abstract: A computer system includes a memory for storing instructions executable by a processor and an on-chip trace memory having a plurality of locations for storing trace information that indicates execution flow in the processor. A trace access instruction provides for access to the on-chip trace memory on the processor. The trace access instruction can be a write instruction or a read instruction. Typically, both read and write to the trace memory is provided. The system also has the capability to trace on start or restart of an executable thread by providing to the processor an indication of which executable thread to trace via a debug port. That indicates to the processor to provide trace information when the executable thread starts. When execution of the executable thread starts, the processor places an identifier corresponding to the executable thread into the trace memory to indicate that subsequent entries placed into the trace memory are part of said executable thread.

Abstract: A general purpose register stores a 16-bit fixed length instruction. A bypass circuit speedily outputs the result of a comparison instruction when the next conditional branch instruction is executed. An ALU performs a logic process and so forth. A high speed multiplying device/high speed dividing device performs an arithmetic operation at high speed. An address calculating portion calculates an address. An instruction decoder/pipeline controlling portion decodes an instruction and controls a pipeline. A dedicated control register is used as an interrupt stack pointer or the like. An interrupt controller performs a multiple interrupt process. A coprocessor bus is disposed independently from a data bus.

Abstract: A method and apparatus to accelerate variable length decode is disclosed. The system includes a logic device to receive a bit stream of variable length encoded information. The logic device outputs a fixed length value corresponding to a variable length code received as part of the bit stream of the variable length encoded information. The system also includes a processor to receive the fixed length value. The processor to performs a write of a coefficient to a system memory device, the coefficient corresponding to the fixed length value received from the logic device.

Abstract: An integrated circuit in which the address and data inputs for a clock register to program a clock is also used for device ID and revision number. A shadow register is provided which is accessible to output the ID and revision number when (1) the regular clock register is addressed, and (2) a particular data input for activating the shadow register appears on the data input to the clock register.

Abstract: A parallel processor apparatus capable of reducing the power consumption when converting serial data to parallel data and, at the same time, capable of improving an operating speed, wherein a data input register for converting serial data to parallel data is divided and data inputting means of a plurality of blocks are constituted and wherein detection circuits for detecting the time of input and the time of output of the pointer data in the data inputting means are provided and switch circuits for connecting the related data inputting means and a serial data input line only for a period from the time of input to the time of output of the pointer data detected by the detection circuit are provided.

Abstract: A coordinate input device includes an upper electrode composed of a transparent resistive layer formed on the lower surface of a flexible transparent film, a lower electrode composed of a transparent resistive layer formed on the upper surface of a substrate composed of transparent glass, a thin film composed of a transparent insulating material having a plurality of holes, and spacers composed of an insulating material provided on the thin film. The upper electrode and the lower electrode are opposed to each other with the spacers therebetween so that the upper electrode and the lower electrode conduct when they are brought into contact with each other through the holes, and the thin film has a lower refractive index than that of the lower electrode.

Abstract: In a load/store unit within a microprocessor, load and store instructions are executed out of order. The load and store instructions are assigned tags in a predetermined manner, and then assigned to load and store reorder queues for keeping track of the program order of the load and store instructions. Then when new load or store instructions are issued, the new load or store instructions are compared to entries within the load and store reorder queues to detect out of order problems.

Abstract: A split directory-based cache coherency technique utilizes a secondary directory in memory to implement a bit mask used to indicate when more than one processor cache in a multi-processor computer system contains the same line of memory which thereby reduces the searches required to perform the coherency operations and the overall size of the memory needed to support the coherency system. The technique includes the attachment of a “coherency tag” to a line of memory so that its status can be tracked without having to read each processor's cache to see if the line of memory is contained within that cache. In this manner, only relatively short cache coherency commands need be transmitted across the communication network (which may comprise a Sebring ring) instead of across the main data path bus thus freeing the main bus from being slowed down by cache coherency data transmissions while removing the bandwidth limitations inherent in other cache coherency techniques.

Abstract: The present invention provides a system and method for improving the performance of general purpose processors by expanding at least one source operand to a width greater than the width of either the general purpose register or the data path width. In addition, the present invention provides several classes of instructions which cannot be performed efficiently if the operands are limited to the width and accessible number of general purpose registers. The present invention provides operands which are substantially larger than the data path width of the processor by using a general purpose register to specify a memory address from which at least more than one, but typically several data path widths of data can be read. The present invention also provides for the efficient usage of a multiplier array that is fully used for high precision arithmetic, but is only partly used for other, lower precision operations.

Abstract: A testing system includes a testing hardware subsystem which can perform testing under a plurality of testing modes. Each testing mode corresponds to the operation of a particular version of a tester. A control subsystem is coupled to the testing hardware subsystem. The control subsystem can direct the testing hardware subsystem to test under one of the plurality of testing modes at a given moment.

Abstract: A method and apparatus for bypassing defective cache memory locations on-board a microprocessor integrated circuit chip, which includes a processor, a cache memory, a store buffer, a tag RAM, and a comparator. The cache memory has a plurality of valid cache memory locations and at least one defective cache memory location. The store buffer has buffer entries and redundancy entries for storing data sent by the processor for storage in the cache memory. The tag RAM has buffer tag entries for storing addresses of data stored in the buffer entries and redundancy tag entries that store addresses of defective cache memory locations in the cache memory. The comparator compares addresses of data sent by the processor for cache memory storage with addresses stored in the redundancy tag entries.